Photomask and integrated circuit manufactured by automatically eliminating design rule violations during construction of a mask layout block

Abstract

A photomask and integrated circuit manufactured by eliminating design rule violations during construction of a mask layout block are disclosed. A photomask includes a substrate and a patterned layer including at least one feature formed on at least a portion of the substrate. The feature is defined in a mask pattern file generated by analyzing a selected position for a polygon during construction of a mask layout block and determining if the selected position creates a design rule violation in the mask layout block based on a design rule from a technology file. The mask pattern file is further generated by automatically preventing the polygon from being placed in the mask layout block at the selected position if the design rule violation exists.

Description

RELATED APPLICATIONS [0001] This application is a continuation of U.S. patent application Ser. No. 10 / 180,165, filed Jun. 26, 2002 and entitled “PHOTOMASK AND INTEGRATED CIRCUIT MANUFACTURED BY AUTOMATICALLY ELIMINATING DESIGN RULE VIOLATIONS DURING CONSTRUCTION OF A MASK LAYOUT BLOCK,” now U.S. Pat. No. ______; which is a continuation-in-part of U.S. patent application Ser. No. 09 / 634,713, filed Aug. 7, 2000 and entitled “AUTOMATIC DESIGN RULE VIOLATIONS ELIMINATION, WHILE CONSTRUCTING MASK LAYOUT DATABASE (IC LAYOUT), METHOD AND COMPUTER SOFTWARE,” now abandonedTECHNICAL FIELD OF THE INVENTION [0002] This invention relates in general to the field of photolithography, and more particularly to photomask and integrated circuit manufactured by automatically eliminating design rule violations during construction of a mask layout block. BACKGROUND OF THE INVENTION [0003] Over the past several years, the number of transistors in a semiconductor device has increased dramatically. Due to t...

AI Technical Summary

Benefits of technology

[0007] In accordance with the present invention, the disadvantages and problems associated with eliminating design rule violations on a photomask have been substantially reduced or eliminated. In a particular embodiment, a photomask is formed by using a mask pattern file created by automatically preventing a polygon from being placed in a selected position in a mask layout block if a design rule violation is identified.

[0010] Important technical advantages of certain embodiments of the present invention include a clean-by-construction (CBC) tool that prevents design rule violations from being created during the construction of a mask layout block. A layout designer may move a cursor on a display device over a polygon in order to select the polygon. The CBC tool highlights an area that may represent a space in the layout block where polygons may be placed without violating any of the design rule constraints contained in a technology file. If the layout designer attempts to move the polygon outside of the highlighted area, the CBC tool prevents the layout designer from placing the polygon in the desired position and automatically places the polygon in a position located inside the highlighted area. The mask layout block, therefore, may be created free of design rule violations.

[0011] Another important technical advantage of certain embodiments of the present invention includes a CBC tool that reduces the design time for an integrated circuit. In a typical integrated circuit design process, a design rule check (DRC) tool analyzes a mask layout file for design rule violations and identifies any violations in an output file. A layout designer may use the output file to manually eliminate the identified design rule violations. In contrast, the present invention may eliminate design rule violations from a mask layout block before the mask layout block is converted into a mask layout file. The time needed to complete the design process for the integrated circuit, therefore, may be substantially reduced since the steps of checking the layout with a DRC tool and correcting the identified design rule violations may be eliminated.

Problems solved by technology

The large number of design rules adds complexity to the layout design process because the layout designer may have to memorize or constantly look up the design rules to place polygons in the mask layout database.

Since the process may be completely manual, the layout designer may create design rule violations during the construction of the mask layout database.

The process of iteratively correcting the design rule violations may take several hours or even days to complete and can increase the time needed to design the integrated circuit.

The additional time required to complete layout may also delay the production of a photomask set used to fabricate the integrated circuit.

Images