Changing scan cell output signal states with a clock signal

Abstract

A test cell (12) provides boundary scan testing in an integrated circuit (10) The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously.

Description

RELATED APPLICATIONS[0001] This Application is related to co-pending Application for U.S. Pat. Ser. No. ______, filed ______, entitled "Testing Buffer / Register", incorporated herein by reference.[0002] This Application is related to co-pending Application for U.S. Pat. Ser. No. ______, filed ______, entitled "Enhanced Test Circuit", incorporated herein by reference.TECHNICAL FIELD OF THE INVENTION[0003] This invention relates in general to integrated circuits, and more particularly to a test cell used in an integrated circuit for providing a boundary scan test structure.BACKGROUND OF THE INVENTION[0004] Due to advances in the fields of board interconnect technology, surface mount packaging and IC density, board level testability is becoming increasingly complex. The combination of advanced board interconnect technology, such as buried wire interconnects and double-sided boards, along with surface mount packaging creates problems for in-circuit testing of the boards. In-circuit testi...

AI Technical Summary

Benefits of technology

[0007] In accordance with the present invention, a boundary scan test system is provided which substantially eliminates the disadvantages and problems associated with prior testing systems.

[0009] The present invention provides a variety of functions for testing purposes. The test cell is operable to both reserve data inputs and control data outputs to and from the cell. The test cell may operate in two modes: "normal" mode and "testing" mode. In normal mode, the test cell provides a data path through which inputs and outputs may propagate freely through the test cell. While in the normal mode, the test cell can also load and shift test data, remain in an idle state, or toggle test data without disturbing the normal operation of the integrated circuit. Further, while in normal mode, a predetermined test data bit may be inserted into the data stream. Also, the test cell may perform a self-test while in the normal mode to insure correct operation of the test cell.

[0011] The present invention provides significant advantages over the prior art. First, the test cell of the present invention may be used to perform internal and external boundary testing simultaneously, in order to reduce overall test time. Second, the test cells are capable of sampling or inserting data at the boundary during normal operation of the host integrated circuit. Third, the test cell is synchronous in operation with a free running test clock. Fourth, the present invention provides a method of toggling an IC's output buffers, independent of the IC's application logic, in order to achieve parametric measures and to facilitate boundary test. Fifth, the test cell provides self-testing capabilities.

Problems solved by technology

Due to advances in the fields of board interconnect technology, surface mount packaging and IC density, board level testability is becoming increasingly complex.

The combination of advanced board interconnect technology, such as buried wire interconnects and double-sided boards, along with surface mount packaging creates problems for in-circuit testing of the boards.

As board density (the number of ICs on a board) increases, the process of probing the board using traditional techniques becomes more difficult, due to the lack of physical access.

When such test is being applied to one IC on a board, neighboring ICs, whose output buffers are tied to the same nodes, may be damaged.

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