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High speed storage demand reducing low density correction code decoder

A technology of low-density check code and storage requirements, applied in the field of forward error correction devices, which can solve the problems of increased decoder area and reduced decoding rate, and achieve the goals of reducing storage requirements, increasing decoding rate, and saving message storage requirements Effect

Inactive Publication Date: 2006-08-23
NANJING UNIV
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AI Technical Summary

Problems solved by technology

However, it is necessary to increase the memory to save the intermediate results in the decoding process, which increases the area of ​​the decoder and reduces the decoding rate.
So far, there is no structure that can solve these problems well

Method used

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  • High speed storage demand reducing low density correction code decoder
  • High speed storage demand reducing low density correction code decoder
  • High speed storage demand reducing low density correction code decoder

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Embodiment Construction

[0061] A high-speed low-density check code decoder for reducing memory requirements of the present invention, it includes a parameter node calculation unit VPU module, a check node calculation unit CPU module and a control logic module; a parameter node calculation unit ( VPU) receives the sequence to be decoded, stores the original information and starts iterative decoding. During the iterative decoding process, the CPU module and the VPU module transmit information to each other, perform row operations and column operations respectively, and store the verification operation results by the CPU; control logic The module controls the cyclic operation of the VPU module and the CPU module, and outputs legal codewords obtained by decoding.

[0062] Principle of the present invention and the algorithm adopted are described as follows:

[0063] It is assumed that the check matrix H is composed of c×t sub-matrices, and each sub-matrix is ​​a P×P square matrix. Then the decoder inclu...

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Abstract

Present invention discloses a high-speed memory requirement reduced low density check code decoder. It contains parameter calculating unit VPU module, verification node computing element CPU module and control logic module, wherein VPU module receiving decode sequence, memory said original information and starting iteration decode, in iterate decode process, CPU module and VPU module mutually transferring information each to proceed line and row operation, CPU storing verification operation result, controlling logical module to VPU module and CPU module cycle operation control, and outputting decode to obtain legal code word. Said invention fully utilizes minimal and decode algorithm to reduce memory requirement and height parallel to raise decode rate to shift LDPC code, saving message storage requirement and reaching faster decode speed and higher throughput rate.

Description

1. Technical field [0001] The invention belongs to a forward error correction device in a digital communication system, can be used in a modern communication system whose channel encoding method is LDPC code, and is especially suitable for a communication system requiring high decoding speed and high throughput rate. 2. Background technology [0002] The transmission of data in the communication system often causes various errors due to a series of reasons such as noise. Due to the existence of these errors, the rate and quality of information transmission are greatly limited. Therefore, communication systems generally use signal coding and decoding techniques to ensure reliable communication over noisy communication channels. The ideal goal of coding techniques is to reach Shannon's limit in communication systems. Among the currently existing coding methods, the Low Density Parity Check (LDPC) coding method has shown coding performance close to the Shannon limit in some ca...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/11H03M13/00
Inventor 高明伦沙金李丽张仲金李伟何书专
Owner NANJING UNIV
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