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Manufacture of semiconductor device

A manufacturing method and semiconductor technology, applied in the direction of semiconductor/solid-state device manufacturing, transistors, electrical components, etc., to achieve the effect of suppressing the increase of resistance value

Inactive Publication Date: 2005-07-27
KK TOSHIBA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This is more serious when the impurity in the LDD region is low concentration

Method used

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  • Manufacture of semiconductor device
  • Manufacture of semiconductor device
  • Manufacture of semiconductor device

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no. 1 Embodiment approach

[0038] figure 1 It is a main part of the semiconductor device according to the first embodiment of the present invention, and is a cross-sectional view showing a low-concentration impurity region before forming a deep source and a deep drain. A part of this low-concentration impurity region becomes a low-concentration impurity region thereafter.

[0039] In this embodiment mode, low-concentration impurity regions 10 , 20 , 30 , and 40 having different junction depths are formed on the same semiconductor substrate (for example, Si substrate) 1 . The knot depth satisfies the relationship of 10>20>30>40.

[0040] On the surface of the semiconductor substrate 1, an element isolation region 2 is formed by, for example, an STI (Shallow Trench Isolation: Shallow Trench Isolation) method in order to isolate and form the element regions 14, 24, 34, and 44 of the respective MOS transistors. Thus, the element regions 14 , 24 , 34 , and 44 are formed. The element isolation region 2 is ...

no. 2 Embodiment approach

[0064] Figure 13 It is a sectional view showing main parts of the semiconductor device according to the second embodiment of the present invention.

[0065] In this embodiment mode, low-concentration impurity regions 10 , 20 , 50 , and 60 having different junction depths are formed on the same semiconductor substrate 1 . The knot depth satisfies the relationship of 10>20>50. In addition, low-concentration impurity region 50 and low-concentration impurity region 60 have substantially the same junction depth.

[0066] The low-concentration impurity region 50 and the low-concentration impurity region 60 differ in the depth of the concentration peak during impurity ion implantation (hereinafter referred to as the peak depth of implanted impurity concentration). Figure 14 It is a graph showing the peak depths of implanted impurity concentrations in the low-concentration impurity region 50 and the low-concentration impurity region 60 . exist Figure 14 In , the dotted line ind...

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Abstract

The present invention provides a manufacturing method of semiconductor devices, which can suppress a decline of impurity density in LDD region with shallow junction depth. The method in which a plurality of MOS transistors are formed on a semiconductor substrate of semiconductor devices, includes a process of forming a plurality of gate electrodes on the semiconductor substrate corresponding to each MOS transistor, and a process of forming LDD regions on surface of the semiconductor substrate at both sides of each MOS transistor according to depth order of junction depth of LDD regions of the above-mentioned MOS transistors.

Description

technical field [0001] The present invention relates to a manufacturing method of a semiconductor device, in particular to a manufacturing method of a semiconductor device including a MOS (Metal Oxide Semiconductor) transistor having an LLD (Lightly Doped Drain) structure. Background technique [0002] With the high integration and miniaturization of semiconductor integrated circuits, it is required to suppress the short channel effect and improve the driving capability of MOS transistors provided in semiconductor integrated circuits. Therefore, LDD structures are generally used for MOS transistors. [0003] In the LDD structure, a low-concentration impurity region (LDD region) is provided at the ends of the source region and the drain region. Generally, the LDD region is formed by ion-implanting low-concentration impurities in advance using the gate electrode as a mask before forming the sidewall insulating film of the gate electrode. [0004] However, a plurality of MOS t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L21/8234H01L27/088
CPCH01L21/823418H01L21/823481H01L29/6659
Inventor 莲见良治宫下桂
Owner KK TOSHIBA
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