Chemical mechanical polishing of copper-oxide damascene structures

Abstract

The present invention provides a method for chemical mechanical polishing of a metallic damascene structure comprising: an insulating layer having grooves on a wafer; and a metal layer having a lower portion and a metal layer positioned within the grooves of the insulating layer Covering the lower part and the upper part of the insulating layer. The method includes: a first step of planarizing the upper portion of the metal layer; and a second step of polishing the insulating layer and the lower portion of the metal layer. In a first step, the wafer and the polishing pad are loaded together in contact mode by applying a pressure p between the wafer and the polishing pad and creating a relative velocity v to increase the metal removal rate. In a second step, in a steady state mode, the lower portions of the insulating and metal layers are polished to form individual metal lines in the grooves with minimal dishing of the metal lines and overpolishing of the insulating layer.

Description

[0001] This application claims priority to US Provisional Patent Application No. 60 / 263,813, filed January 23, 2001, the entire disclosure of which application is hereby incorporated by reference. technical field [0002] The present invention relates generally to chemical mechanical polishing (CMP) in semiconductor manufacturing. More specifically, the present invention relates to CMP of copper-oxide damascene structures to increase material removal rates and reduce copper dishing and oxide overpolishing. Background technique [0003] Continued advances in very large scale integration (ULSI) of semiconductor devices require the design and fabrication of very small devices. The metallization pattern technology for interconnection (interconnect) in the prior art is not enough to cope with the new type of integrated circuit (IC). According to calculations, for a CMOS circuit with a gate size smaller than 0.25 μm, the resistance-capacitance (RC) delay caused by the metallizati...

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Problems solved by technology

One problem with this phenomenological model is that the correlation between polishing rate and pattern geometry varies with pattern design, so the friction mechanism for planarization in this model is unclear

Although several semi-empirical models have been proposed, the fundamentals of dishing and overthrowing and their relationship to pattern geometry and material properties have not been fully understood

In addition, since most experiments were performed on large-scale components, the results and related problems, such as severe dishing on 100 μm components, will not be suitable for current sub-0.25 μm (sub-quarter micron) Circuit design, in this case, must focus on scaling issues

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