Semiconductor device and method for making same

Abstract

Disclosed is a manufacturing method of a semiconductor device. An LDD structure and a silicide layer are formed without a reduction in thickness of a silicon substrate or a carbon contamination. Forming a spacer on a sidewall of a gate electrode is performed in two process steps, i.e. dry-etching and wet-etching. Also, a silicon nitride film used as a buffer film in injection of high dose of impurities is removed by wet-etching. As a result, the reduction in thickness of the silicon substrate and the carbon contamination can be prevented. In addition, variation in depth of the high and low impurity concentration regions and silicide forming region with locations on the wafer can be suppressed because of high selection ratio available with the wet-etching.

Description

technical field [0001] The present invention relates to a manufacturing method of a semiconductor device, in particular to a manufacturing method of a semiconductor device having an LDD (Lightly Doped Drain) structure and forming a silicide layer on a silicon substrate or a gate electrode. Background technique [0002] With the advancement of miniaturization of semiconductor devices, there arises a problem that the characteristics of MOS transistors are degraded by the short channel effect. In response to this, a technology called an LDD (Lightly Doped Drain) structure has been developed and utilized. In addition, reducing the size of the gate electrode, source, and drain regions also raises the problem of increased resistance of the gate electrode, source, and drain regions. As a method to deal with this problem, a silicide layer called metal silicide (Silicid) is used in which a silicide layer obtained by reacting silicon and a transition metal is formed by self-alignment...

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Problems solved by technology

[0021] However, wafers obtained by growing thin silicon crystals on insulators, such as wafers with SOI (Silicon On Insulator) structures that have been developed and used in recent years, pose a very serious problem.

Since the thickness of silicon-on-insulator is about 50nm to 100nm, it is very thin, so if Figure 15 As shown, the silicon reduction of 34nm will lead to a large reduction in the depth of the impurity region or silicide layer

As a result, the characteristics of the transistor deteriorate

Sometimes the impurity region or silicide layer of the depth necessary for the operation of the transistor cannot be obtained, so the transistor cannot be operated

[0022] In addition, during dry etching, variations in the etching rate and selectivity will occur depending on the position in the wafer plane. As a result, there is also a problem that the resistance of the source, drain region, or gate electrode in the wafer plane is generated. deviation

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