MOSFET and its manufacture

Abstract

The present invention is MOSFET and its manufacture. The MOSFET features the semiconductor substrate with one channel, the passage area being one thin doped semiconductor layer across the channel, and the gate located inside and over the channel and around the passage area with gate dielectric layer in between. The manufacture process includes the steps of: providing one semiconductor substrate and forming one channel on the substrate; filling the channel with sacrificed layer, forming one doped semiconductor layer, defining one element area across the sacrificed layer and exposing partial sacrificed layer; removing the sacrificed layer to expose the lower element area surface over the channel and forming one gate dielectric layer on the surface of element area and the channel; forming one conducting layer on the gate dielectric layer, filling the channel and defining the conducting layer to form gate in and over the channel; and forming source and drain beside the gate.

Description

technical field [0001] The present invention relates to a structure of a semiconductor device (Semiconductor Device) and a manufacturing method thereof, and in particular to a metal oxide semiconductor field effect transistor (MOSFET) and a manufacturing method thereof. Background technique [0002] As the linewidth of the metal oxide semiconductor (MOS) process shrinks, the leakage current between the source (Source) and the drain (Drain) away from the gate (Gate) also increases. Although this leakage current can be reduced by a thinner gate dielectric layer (Gate Dielectric), when the process line width drops below 0.1 μm, even a very thin gate dielectric layer cannot reduce the leakage current . For this problem, Professor Hu Zhengming (Chenming Hu, transliteration) of the University of California, Berkeley pointed out two solutions. One is to use an extremely thin semiconductor substrate to make MOSFETs, so that there is no longer any gate in the substrate. The second ...

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Problems solved by technology

Second, when forming the raised source and drain sidewall spacers of the FinFET, the spacer material (silicon nitride) on the sidewalls of the fin-shaped silicon layer is removed by over-etching, so the fin-shaped silicon layer Defects will be generated at the sidewall, that is, the surface properties of the channel area will deteriorate, which will affect the performance of the device

Third, in order to reduce the source and drain resistance of the FinFET, the raised source and drain are used, and the process conditions are not easy to control

Fourth, because FinFET is a vertical structure component, the subsequent planarization process is not easy to carry out

Fifth, since the width of the Fin-shaped silicon layer 120 of the FinFET must be very narrow in order to reduce the leakage current, it needs to be defined by the electron beam lithography technology that has not yet been mass-produced, and the subsequent non-equal It is not easy to control the etching process

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