Zero-delay buffer circuit for spread spectrum clock system and method

Abstract

A clock recovery circuit and a method for reduced electromagnetic emission (EMI) and increasing an attainable clock frequency includes a spread spectrum clock (SSC) generator that receives an input clock signal and generates a frequency-modulated clock signal, and a zero-delay buffer circuit that receives and buffers said modulated clock frequency signed to generate an output clock signal. The frequency-modulated clock signal and the output clock signal are phase-aligned such that there is no phase difference between the output clock signal and the modulated frequency clock signal. The clock recovery circuit also includes a delay-locked loop (DLL) circuit that reduces related art jitter and skew characteristics, and a phase detector circuit that eliminates phase ambiguity problems of a related art phase detector.

Description

technical field [0001] The present invention relates to a zero-delay buffer circuit and method thereof for a spread spectrum clock (SSC) system, and more particularly to a zero-delay buffer circuit with a delay-locked loop (DLL) based zero-delay buffer. Background technique [0002] In the prior art to improve the efficiency of computer systems, it is desirable to increase the processing speed by increasing the clock frequency to allow the central processing unit (CPU) to run at a higher frequency. Increasing the clock frequency also increases the frequency of the computer system, and likewise, peripherals (eg, memory, graphics cards) can also run at higher frequencies. However, as the clock frequency increases, the increased peak amplitude results in increased electromagnetic emissions (EMI). As a result, EMI limits the increase of clock frequency in the prior art. [0003] A prior art known as spread spectrum clocking (SSC) reduces EMI and modulat...

AI Technical Summary

Problems solved by technology

However, even the state-of-the-art SSC technology with optimal feedback loop bandwidth and phase angle still has jitter and phase offset errors, such as Zhang, Michael T.'s, Notes on SSC and Its Timing Impacts, (SSC Notes and Its Timing Impacts Impact) Rev. 1.0, February 1998, pp. 1-8, listed here by reference

Therefore, jitter and phase offset issues limit the improvements in clock frequency that can be achieved with existing SSC technology

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