CMOS sensor matrix with memory interface

A memory interface and sensor array technology, applied in the field of image sensors, can solve the problems of speed pixel transmission rate limitation, data transmission bottleneck, etc.

Inactive Publication Date: 2002-08-14
匹克希姆公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The speed of conventional digital imaging systems is limited by the pixel transfer rate of the pixel data bus 12, and this pixel data bus becomes the data transfer bottleneck of the imaging system

Method used

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  • CMOS sensor matrix with memory interface
  • CMOS sensor matrix with memory interface

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Embodiment Construction

[0023] An image sensor according to the invention includes an integrated on-chip memory and a memory interface for outputting pixel data. By including a memory interface in the image sensor of the present invention, the image sensor can be directly connected to a memory interface port of an external image processing unit. The image processing unit is able to access the image sensor using conventional memory access protocols. In some embodiments, the image sensors of the present invention support SRAM, DRAM, or RAMBUS memory interfaces. The image sensor of the present invention facilitates high-speed pixel readout between the image sensor and an image processing device by providing on-chip memory and a memory interface in the image sensor. Pixel data transfer bandwidth is limited only by the speed of the memory interface. Also, by using the memory interface of the image sensor for sensor readout, the image processing device can access the pixel data in the image sensor, which...

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Abstract

An image sensor includes a sensor or a pixel array, a data memory, and a logic circuit, all fabricated on the same integrated chip. The sensor or pixel array outputs digital signals as pixel data representing an image of a scene. The data memory is coupled to the sensor or pixel array for storing the pixel data. The logic circuit is coupled to the data memory and provides a memory interface for exporting the pixel data. The memory interface can be one of a SRAM, a DRAM or a packet protocol synchronous DRAM interface. Including a memory interface in the image sensor allows the image sensor to be coupled directly to the memory interface port of an external image processing unit. The image processing unit can access the image sensor using conventional memory access protocols, thus improving the efficiency and reducing the operational complexity of the image processing unit.

Description

technical field [0001] The present invention generally relates to an image sensor system; in particular, the present invention relates to an image sensor including a memory interface. Background technique [0002] Cross-references to related applications [0003] This invention is a continuation of the following co-pending U.S. Patent Application No. 09 / 567,638 (Attorney Docket No. PIXI0002), entitled "Integrated Digital Pixel Sensor With Detection Area and Digital Storage Area," which was published in 2000 Filed on May 9, 2009 and the inventors are David Yang et al., two of whom are also co-inventors of the present invention. Background of the invention [0004] Digital photography is one of the most exciting technologies to emerge in the past few years. With the right hardware and software (and a little knowledge), anyone can put the principles of digital photography into practice. For example, digital cameras are at the forefront of digital photography. Along with e...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/146G06F12/00G06T1/00G06T1/60H04N1/00H04N1/028H04N5/232H04N5/335H04N7/14
CPCH04N3/155H04N2201/0068H04N1/00307H04N7/142H04N5/232H04N5/335H04N23/665H04N25/76H04N23/60H04N25/00
Inventor O·O·埃韦德米邓中韩R·J·莫塔杨晓东
Owner 匹克希姆公司
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