MOSFET and its manufacture

Abstract

A metal oxide semiconductor field effect transistor and its manufacturing method, the metal oxide semiconductor field effect transistor is characterized by a trench in the semiconductor substrate, and the channel region is a doped semiconductor across the trench thin layer, and the gate is located in the trench and above the trench, and surrounds the channel region through the gate dielectric layer. The steps of another manufacturing method are as follows: first, a semiconductor substrate is provided, and then a trench is formed on it. Then fill up the trench with a sacrificial layer, form a doped semiconductor layer, and define it to form an element region. The element region crosses the sacrificial layer and exposes a part of the sacrificial layer. Then the sacrificial layer is removed to expose the lower surface of the element region above the trench, and then a gate dielectric layer is formed on the surface of the element region and the trench. Next, a conductor layer is formed on the gate dielectric layer and filled into the trench, and then the conductor layer is defined to form a gate located in and above the trench. Then, a source and a drain are formed on both sides of the gate.

Description

technical field [0001] The present invention relates to a structure of a semiconductor device (Semiconductor Device) and a manufacturing method thereof, and in particular to a metal oxide semiconductor field effect transistor (MOSFET) and a manufacturing method thereof. Background technique [0002] As the linewidth of the metal oxide semiconductor (MOS) process shrinks, the leakage current between the source and the drain away from the gate also increases. Although this leakage current can be reduced by a thinner gate dielectric layer (Gate Dielectric), when the process line width drops below 0.1 μm, even a very thin gate dielectric layer cannot reduce the leakage current . For this problem, Professor Hu Zhengming (Chenming Hu, transliteration) of the University of California, Berkeley, USA pointed out two solutions. One is to use an extremely thin semiconductor substrate to make MOSFETs, so that there is no longer any gate in the substrate. The second is to form a double...

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Problems solved by technology

Second, when forming the raised source and drain sidewall spacers of the FinFET, the spacer material (silicon nitride) on the sidewalls of the fin-shaped silicon layer is removed by over-etching, so the fin-shaped silicon layer Defects will occur on the sidewall, that is, the surface properties of the channel region will deteriorate, which will affect the performance of the device

Third, the process conditions of the raised source and drain used to reduce the source and drain resistance of FinFET are not easy to control

Fourth, because FinFET is a vertical structure component, the subsequent planarization process is not easy to carry out

Fifth, since the fin-shaped silicon layer 120 of the FinFET must be narrow in width to reduce the leakage current, it needs to be defined by electron beam lithography technology that has not yet been mass-produced, and the subsequent non-equal It is not easy to control the etching process

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