Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Soldering of semiconductor chip to substrate

A chip welding and semiconductor technology, which is applied in the field of welding semiconductor chips and substrates, can solve the problems of increasing the thermal resistance of the chip and the package, and achieve the effects of low welding temperature, reducing thermal resistance, and reducing the risk of poor solder connection.

Inactive Publication Date: 2005-04-06
INFINEON TECH AG
View PDF0 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, a junction of this thickness increases the thermal resistance between the chip and the package to unacceptable levels

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0028] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0029] Gold-tin soldering requires solderable surfaces on both the substrate and the semiconductor chip. In the case of semiconductor chips, this requirement is met by coating the otherwise finished semiconductor chip with an adhesive layer on the semiconductor, which may be eg silicon. A solderable layer is disposed on the adhesive layer, and an anti-oxidation layer is arranged on the solderable layer. This adhesion layer may for example comprise TiW (titanium-tungsten), while the solderable layer may comprise Ni (nickel) and the anti-oxidation layer may comprise Au (gold). The bonding layer can also consist of pure titanium, in which case the solderable layer can consist of platinum and the anti-oxidation layer consist of gold.

[0030] The thickness of the adhesive layer can be in the range of 1000-1500 Å, the thickness of the solderable layer can be in the range of 1000-1500 Å, and the thickness of the anti-oxidat...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
thicknessaaaaaaaaaa
Login to View More

Abstract

The present invention relates to a method of soldering a semiconductor chip to a substrate, such as to a capsule in an RF-power transistor, for instance. The semiconductor chip is provided with an adhesion layer consisting of a first material composition. A solderable layer consisting of a second material composition is disposed on this adhesion layer. An antioxidation layer consisting of a third material composition is disposed on said solderable layer. The antioxidation layer is coated with a layer of gold-tin solder. The chip is placed on a solderable capsule surface, via said gold-tin solder. The capsule and chip are exposed to an inert environment to which a reducing gas is delivered and the capsule and chip are subjected to a pressure substantially beneath atmospheric pressure whilst the gold-tin solder is heated to a temperature above its melting point. The gas pressure is increased whilst the gold-tin solder is molten and the temperature is lowered when a predetermined gas pressure is exceeded, so that the gold-tin solder will solidify.

Description

field of invention [0001] The present invention generally relates to a method and devices produced by said method of bonding a semiconductor chip to a substrate, and more particularly to a method of bonding said semiconductor chip to an enclosure in a radio frequency power transistor. background of the invention [0002] Currently, chips are mounted in RF power transistors and RF power modules using a fusible gold-silicon bonding process. The capsules used are often alloyed with nickel and a relatively thick layer of gold (2-5 μm). A very thin layer of gold is provided on the bottom surface of the chips (transistors, resistors and capacitors) to be placed in the package. The function of this gold layer is to prevent oxidation of the bottom surface of the chip. When gold-silicon is used, the capsule is heated to a temperature of 400-450°C, and the chips are placed on the capsule individually and rubbed back and forth until an alloy is formed between the silicon in the chip ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L25/00H01L21/52H01L21/60
CPCH01L24/29H01L2924/01074H01L2924/01002H01L2924/1579H01L2924/01061H01L2924/014H01L2224/29144H01L2924/0105H01L2924/01322H01L2924/01029H01L2224/83805H01L2924/01059H01L2924/0132H01L2924/01013H01L24/83H01L2924/01082H01L2224/29111H01L2924/01056H01L2924/01079H01L2924/01004H01L2224/83801H01L2924/01015H01L2924/19041H01L2224/8319H01L2924/01006H01L2924/01078H01L2924/19043H01L2924/00011Y10T428/12528H01L2924/01014H01L2924/00H01L2924/01022H01L2924/3512H01L2924/00015H01L2924/00012H01L2224/83205H05K3/34
Inventor L·-A·奥洛夫松
Owner INFINEON TECH AG
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products