Instruction processing method and device, microcontroller and readable storage medium

Abstract

The invention relates to the technical field of data processing, and provides an instruction processing method and device, a microcontroller and a medium, and the method comprises the steps: parsing an instruction read from a memory; after the instruction is analyzed to be a branch instruction, the types of the instruction are classified, and the offset of the instruction is calculated; calculating a next prefetch address according to the type of the instruction and the offset of the instruction; and writing the instruction into the corresponding cache region according to the type of the instruction and the next prefetch address of the instruction, and then prefetching the instruction. According to the method, the instructions are analyzed and classified, the instructions are cached to the corresponding cache regions according to the types of the instructions, and the instruction fetching address of the next instruction is calculated, so that the instruction processing efficiency is effectively improved, the system performance is further improved, and the influence on the system performance due to the increase of read delay is reduced.

Description

technical field [0001] The present application relates to the technical field of data processing, and in particular, to an instruction processing method, device, microcontroller and readable storage medium. Background technique [0002] With the increasing demand for MCUs in the Internet of Things, industrial control, and automotive electronics, MCUs with CORTEX-M series processors as the core have begun to be widely used in the above-mentioned fields. As a microcontroller, MCU pursues more low cost and low power consumption, so the read and write speed of the embedded FLASH or other non-volatile memory used is not high, and it is lower than the access speed of the core. When the core needs to run at a higher clock frequency, it has to increase the read delay for the access to achieve the purpose of correctly accessing the memory. Although increasing the read delay can ensure correct access to the memory, it reduces the maximum performance of the processor. Therefore, modul...

AI Technical Summary

Problems solved by technology

[0003] During the process of conceiving and implementing the present application, the inventors of the present application have found at least the following problems: the existing technology stops prefetching when encountering branch instructions, resulting in a small improvement in system performance in complex software; in addition, although the existing There are ways to predict conditional branch instructions, but in the CORTEX-M series processors, the instruction fetch timing will not be very generous. When the processor fetches instructions, fetches data, or accesses peripherals, there will be some clock gaps that do not access memory. , resulting in one or two idle clocks, but not enough to complete two instruction fetch operations. When a conditional branch occurs, it is necessary to select a fetch direction. Once the wrong direction is selected, the processor needs to wait for the current wrong prefetch instruction to complete. Instruction fetching, leading to problems that reduce system efficiency

Images