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Clock planning method and device of programmable device, electronic equipment and storage medium

A clock circuit and clock technology, applied in the direction of instruments, computer components, electrical digital data processing, etc., can solve the problems of small amount of calculation, high flexibility, etc., and achieve the effect of reducing crossover, high flexibility, and reasonable placement

Pending Publication Date: 2022-01-11
SHENZHEN PANGO MICROSYST CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Embodiments of the present invention provide a clock planning method, device, electronic equipment, and storage medium for a programmable device, so as to solve the problem that the current clock planning method cannot meet the requirements of a small amount of calculation and high flexibility at the same time.

Method used

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  • Clock planning method and device of programmable device, electronic equipment and storage medium
  • Clock planning method and device of programmable device, electronic equipment and storage medium
  • Clock planning method and device of programmable device, electronic equipment and storage medium

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Embodiment Construction

[0060] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0061] Such as figure 1 As shown, the first embodiment of the present invention is a clock planning method for a programmable device, which includes starting—collecting chip hardware information—determining the connection relationship between each clock circuit unit—aggregating each clock circuit unit Class—Set the planning sequence of each clock circuit—Plan each clock circuit according to the planned planning sequence—Adjust and optimize the planning...

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PUM

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Abstract

The invention discloses a clock planning method and device of a programmable device, electronic equipment and a storage medium, and belongs to the field of integrated circuits. The method comprises starting; collecting hardware information; determining a connection relationship between the clock circuit units; clustering the clock circuit units; setting a planning sequence of each clock circuit; planning each clock circuit according to the formulated planning sequence; adjusting and optimizing the planning result of the whole clock circuit; and ending. According to the method, the clock planning process is simplified, the clock planning speed is increased, the calculation method is simple, the calculation amount is small, the flexibility is high, clock resources can be reasonably placed, the implementation difficulty of clock planning is reduced, the running time is shortened, and the method can adapt to more application scenes.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, relates to field programmable logic device (PLD for short) integrated circuit software tool design technology, in particular to a clock planning method, device, electronic equipment and storage medium for programmable devices. Background technique [0002] At present, the clock circuit units of programmable devices (that is, programmable logic devices) have exceeded 100 million gates, and the operating frequency of the clock circuit has exceeded 1GHz. The clock circuit provides high-frequency clock signals for other ultra-high-speed processing circuits inside the programmable device. In the workflow of logic synthesis, mapping, placement, routing and bit stream generation of EDA software tools for programmable devices, the main role of the clock planning function in the layout stage is to reasonably allocate clock resources of programmable devices and improve the efficiency of programm...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/347G06V10/762G06V10/764
CPCG06F30/347G06F18/23G06F18/24
Inventor 刘世仁谭宇泉夏炜
Owner SHENZHEN PANGO MICROSYST CO LTD
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