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APPARATUS FOR ENHANCING amount of prefetched access data IN MEMORY MODULE

A memory module and data prefetch technology, which is applied in static memory, read-only memory, information storage, etc., can solve the problem that the limit of prefetch quantity cannot be further increased, and achieve the effect of improving performance and increasing the amount of data prefetch

Pending Publication Date: 2021-05-25
PIECEMAKERS TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, there is usually a trade-off between the amount of data prefetch and the chip area, and without greatly increasing the chip area, the traditional cell array architecture of the DRAM chip will have a negative impact on the amount of prefetch. The limit cannot be increased further

Method used

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  • APPARATUS FOR ENHANCING amount of prefetched access data IN MEMORY MODULE
  • APPARATUS FOR ENHANCING amount of prefetched access data IN MEMORY MODULE
  • APPARATUS FOR ENHANCING amount of prefetched access data IN MEMORY MODULE

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Embodiment Construction

[0048] figure 1 According to an embodiment of the present invention, it is a device for increasing the number of data prefetch (prefetch) in a memory (such as dynamic random access memory, etc.) module, wherein the device may include at least a part of the memory module 100 (such as a part or all). For example, the device may include a local memory architecture of the memory module 100 . As another example, the apparatus may include the local memory architecture and associated control mechanisms. As another example, the device may include the entire memory module 100 .

[0049] Such as figure 1 As shown, the memory module 100 may include a memory chip 101 and a second (secondary) semiconductor chip 102, and the memory chip 101 may include a word line (word line, WL) decoder 110, including a plurality of memory cells such as ( A storage cell array 120 with M*N) storage cells (for example, M and N may respectively represent positive integers), and a plurality of bit lines (b...

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Abstract

The invention discloses an apparatus for enhancing the amount of prefetched access data in a memory module. The memory chip included in the memory device comprises a memory cell array, a plurality of bit lines and a plurality of word lines, a plurality of bit line sense amplifier (BLSAs for short), and a plurality of main data lines. The memory cell array may be arranged to store data, and the plurality of bit lines and the plurality of word lines may be arranged to perform access control of the memory cell array. The plurality of BLSAs may sense a plurality of bit-line signals restored from the plurality of memory cells and convert the plurality of bit-line signals into a plurality of amplified signals, respectively. The main data lines may directly output the amplified signals, through selection of CSLs of the BLSAs on the memory chip, to an another semiconductor chip or a secondary semiconductor chip, for performing further processing and using of the memory module, thereby enhancing the prefetch access. The apparatus provided by the invention can increase the data prefetching amount and achieve high-bandwidth data access under the condition of not increasing the size and cost of a chip.

Description

technical field [0001] The present invention relates to a memory device (apparatus) and the management of the memory device, in particular to a method for increasing the amount of prefetch access data in the memory module by means of a local memory architecture in the memory device device and management of this memory device. Background technique [0002] According to the related art, under a fixed storage capacity, reducing the chip area of ​​a memory (memory) such as a dynamic random access memory (Dynamic Random Access Memory, DRAM) is an important consideration. However, in order to achieve the goal of high bandwidth access, it is necessary to increase the prefetch quantity of the DRAM. However, there is usually a trade-off between the amount of data prefetch and the chip area, and without greatly increasing the chip area, the traditional cell array architecture of the DRAM chip will have a negative impact on the amount of prefetch. The limit cannot be increased furthe...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C5/06G11C16/08
CPCG11C5/063G11C16/08
Inventor 王智彬王明弘丁达刚
Owner PIECEMAKERS TECH
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