Ring polynomial multiplier circuit in lattice password encryption and decryption

A technology of polynomial multiplication and lattice cipher, applied in the field of hardware implementation of lattice cipher, which can solve problems such as consuming a large time period and resources, and not being so easy

Pending Publication Date: 2021-05-18
NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
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  • Summary
  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

[0010] Realizing SPM in software can be realized by a simple algorithm of loop judgment, but it is not so easy to realize ring polynomial multiplication in hardware architecture. Multiplication and addition are both modular multiplication and modular addition, which usually consume a lot of time and resources.

Method used

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  • Ring polynomial multiplier circuit in lattice password encryption and decryption
  • Ring polynomial multiplier circuit in lattice password encryption and decryption
  • Ring polynomial multiplier circuit in lattice password encryption and decryption

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Embodiment Construction

[0025] The technical solutions of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0026] For the SPM algorithm, most of the designs are focused on lightweight, that is, for a single or a small number of modular multiplication units according to the following ring polynomial calculation formula:

[0027]

[0028] Continuously reuse a single multiplier unit to calculate the final polynomial coefficients in turn. In addition to the shortcomings of excessive time consumption, this method also has slow data processing speed, that is, low throughput rate, and complex control units when implemented in hardware circuits. The circuit structure of SPM needs multiple modular multiplication units to calculate in parallel in order to obtain higher throughput. In order to understand the calculation process of the integer ring polynomial Schoolbook algorithm more clearly, figure 1 The calculation of the whole algorithm is expanded ...

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Abstract

The invention discloses a ring polynomial multiplier circuit in lattice password encryption and decryption, which has high degree of parallelism, achieves the effects of reducing time period and high throughput rate when FPGA hardware is realized, and simplifies a control unit. Meanwhile, a coefficient of one polynomial multiplication can be expressed by adopting a signed number in combination with specific parameters, two times of multiplication can be completed in the same clock of a single DSP module in the FPGA, module reduction is optimized, the lattice password encryption and decryption efficiency is greatly improved, and resource consumption is reduced.

Description

technical field [0001] The invention belongs to the field of lattice cipher hardware realization, and in particular relates to a ring polynomial multiplier circuit. Background technique [0002] The emergence of quantum computers will pose a great threat to existing cryptosystems. Lattice ciphers are the most promising post-quantum ciphers that can resist quantum attacks. Ring polynomial multiplication is based on RLWE (Ring Learning WithErrors) and MLWE In the (Module Learning With Errors) problem, the calculation of the lattice cipher encryption and decryption operations is the most complex, and the operation that consumes the most resources and time is the key part that affects the performance of the lattice cipher hardware. In the field of integers, given two polynomials a(x), b(x), such as: [0003] [0004] [0005] After multiplying these two polynomials directly, we get the polynomial here [0006] [0007] This method of obtaining the result of multiply...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06N10/00G06F7/72
CPCG06F7/722G06N10/00
Inventor 刘伟强张雨晴姚衎王成华
Owner NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
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