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Semiconductor structure and preparation method thereof

A semiconductor and trench technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve problems such as increased aspect ratio and metal plugs that tend to have gaps or holes

Inactive Publication Date: 2021-04-30
CHANGXIN MEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] Based on this, it is necessary to address the problem that the aspect ratio of the contact hole or the through hole increases, and the metal plug formed when the contact hole or the through hole is directly filled with metal is likely to have defects such as gaps or holes, and to provide a semiconductor Structure and its preparation method

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  • Semiconductor structure and preparation method thereof
  • Semiconductor structure and preparation method thereof
  • Semiconductor structure and preparation method thereof

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Embodiment Construction

[0036] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the associated drawings. A preferred embodiment of the invention is shown in the drawings. However, the present invention can be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present invention will be thorough and complete. It should be noted that the terms "forming", "converting", "filling" and similar expressions used herein are for illustrative purposes only.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field of the invention. The terms used herein in the description of the present invention are for the purpose of describing specific embodiments only, and are not intended to limit the present i...

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Abstract

The invention relates to a semiconductor structure and a preparation method thereof. According to the preparation method of the semiconductor structure, the passivation area of metal in a groove is accurately controlled through ion implantation, then the forming rate of the metal in the groove is reduced, and the forming rate of the metal in the passivation layer is controlled to be slower than that of the metal in the seed layer, so sufficient deposition of the metal in the groove can be promoted, and when the groove with a high depth-to-width ratio is filled, the defects of gaps, holes and the like can be avoided. Meanwhile, a reaction area can be directly defined through ion implantation, the forming area of the metal passivation layer can be accurately controlled, and the control capacity of the technological process is enhanced; and moreover, the metal passivation layer can be used as a barrier layer without adding a removal step, so that the preparation process is simplified.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a preparation method thereof. Background technique [0002] With the continuous development of semiconductor technology, the feature size of semiconductor integrated circuit devices is continuously reduced. Due to the shrinkage of device size, the aspect ratio of contact holes or through holes as interconnect structures is getting larger and larger. When metal filling is performed, the top is pre-sealed before the metal fills the contact hole or via, so that the formed metal plug has defects such as gaps or holes. Contents of the invention [0003] Based on this, it is necessary to address the problem that the aspect ratio of the contact hole or the through hole increases, and the metal plug formed when the contact hole or the through hole is directly filled with metal is likely to have defects such as gaps or holes, and to provide a semi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768H01L23/528
CPCH01L21/76879H01L21/76883H01L21/76834H01L23/5283
Inventor 朱德龙
Owner CHANGXIN MEMORY TECH INC
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