A Neural Network Compilation Method for Storage and Computing Integrated Platform

A neural network and compilation method technology, applied in the field of storage and calculation, can solve problems such as mapping, difficult hardware execution efficiency, difficult network weight once, etc., to achieve the effect of reducing write-back overhead and reducing the number of remapping weights

Active Publication Date: 2022-07-22
SHANGHAI JIAOTONG UNIV
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AI Technical Summary

Problems solved by technology

[0013] 1. It cannot support a variety of neural network programming frameworks, and has not done more explorations in computational graph-level optimization;
[0014] 2. There is no flexible operator optimization and scheduling interface, and a similar mapping method is adopted for all operators. Therefore, for a new specific operator, it is difficult for programmers to maximize the execution efficiency of the hardware;
[0015] 3. Deploy the weights of the entire network on the array at one time, without considering the need to update the weights. In fact, it is difficult to map the weights of the network to the Crossbararray (cross array) at one time due to the limitation of the technology level and the weight scale of the neural network model.

Method used

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  • A Neural Network Compilation Method for Storage and Computing Integrated Platform
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  • A Neural Network Compilation Method for Storage and Computing Integrated Platform

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Embodiment Construction

[0049] The following describes several preferred embodiments of the present invention with reference to the accompanying drawings, so as to make its technical content clearer and easier to understand. The present invention can be embodied in many different forms of embodiments, and the protection scope of the present invention is not limited to the embodiments mentioned herein.

[0050] In the drawings, structurally identical components are denoted by the same numerals, and structurally or functionally similar components are denoted by like numerals throughout. The size and thickness of each component shown in the drawings are arbitrarily shown, and the present invention does not limit the size and thickness of each component. In order to make the illustration clearer, the thicknesses of components are appropriately exaggerated in some places in the drawings.

[0051] by figure 2 The shown hardware structure of the integrated storage-computing accelerator Core is taken as a...

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Abstract

The invention discloses a method for compiling a neural network for an integrated storage and computing platform, which relates to the field of integrated storage and computing. Sub-level intermediate representation; divide operator tasks and bind them with hardware basic units; perform operator-level optimization to reduce the number of times of reading discontinuous memory and the number of weight mappings. The invention optimizes the calculation flow graph and the neural network operator according to the characteristics of integrated computing of storage and computing, reduces the overhead of writing back intermediate results between the graph-level operators, and reduces the number of times that weights need to be remapped when storage and computing resources are insufficient.

Description

technical field [0001] The invention relates to the field of integrated storage and computing, in particular to a neural network compilation method oriented to an integrated storage and computing platform. Background technique [0002] Deep learning has made many breakthroughs in speech recognition, image recognition and other fields. The existing deep neural network needs to complete the calculation in a shorter time and with lower power consumption, which puts forward higher requirements for the deep learning computing chip. Therefore, a non-volatile memory (Non-volatile memory, NVM) such as a memristor has emerged as an integrated storage and computing accelerator for the computing unit. This type of accelerator effectively solves the bottleneck of bandwidth, and has the characteristics of low power consumption and high speed. Its research and development also open up a new field for in-memory computing. [0003] At present, the basic algorithms of artificial intelligenc...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06N3/04G06N3/063G06N3/08
CPCG06N3/063G06N3/08G06N3/045
Inventor 绳伟光师紧想蒋剑飞景乃锋王琴毛志刚
Owner SHANGHAI JIAOTONG UNIV
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