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Six-layer wiring LCP packaging substrate, manufacturing method and multi-chip system-in-package structure

A technology for packaging substrates and substrates, which is used in the manufacture of semiconductor/solid-state devices, electrical components, and electrical solid-state devices to achieve the effects of good compatibility, high electromagnetic shielding, low moisture absorption, water permeability and oxygen permeability

Active Publication Date: 2021-02-09
SOUTHWEST CHINA RES INST OF ELECTRONICS EQUIP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0016] The existing disclosed technology has not yet used LCP to realize the technical solution of packaging substrate and system-in-package structure that meets the system-in-package requirements of multi-chip, high airtightness requirements, high electromagnetic shielding, and highly reliable interconnection.

Method used

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  • Six-layer wiring LCP packaging substrate, manufacturing method and multi-chip system-in-package structure
  • Six-layer wiring LCP packaging substrate, manufacturing method and multi-chip system-in-package structure
  • Six-layer wiring LCP packaging substrate, manufacturing method and multi-chip system-in-package structure

Examples

Experimental program
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Effect test

Embodiment 1

[0079] Such as figure 1 As shown, a six-layer wiring LCP packaging substrate of this embodiment includes:

[0080] 6 layers of patterned metal circuit layers distributed from the surface to the bottom surface, followed by the first layer of patterned metal circuit layer, the second layer of patterned metal circuit layer, the third layer of patterned metal circuit layer, and the fourth layer of patterned metal circuit layer layer, the fifth layer of patterned metal circuit layer and the sixth layer of patterned metal circuit layer; the sixth layer of patterned metal circuit layer is provided with a structure for welding BGA solder balls;

[0081] 5 layers of insulating dielectric layers between adjacent patterned metal circuit layers;

[0082] Located in the insulating dielectric layer between the first patterned metal wiring layer and the second patterned metal wiring layer, with openings facing the multiple blind slots of the first patterned metal wiring layer;

[0083] A p...

Embodiment 2

[0101] Such as Figure 4 As shown, this embodiment provides a method for manufacturing the six-layer wiring LCP packaging substrate 1 as described in Embodiment 1, including the following steps:

[0102] S1, such as Figure 5a As shown, blind holes are laser drilled on the double-sided copper-clad LCP substrate 155 to form third-type blind holes 143 that penetrate and connect the third patterned metal circuit layer 113 and the fourth layer patterned metal circuit layer 114. The blind holes Depth-to-diameter ratio≤1;

[0103] S2, such as Figure 5b As shown, the metallization of blind holes forms the third type of blind holes 143 filled with solid electroplated copper; The electroplating copper process is realized. After hole filling electroplating, the copper plating layer on the surface is thinned to form a third type of blind hole 143 filled with solid electroplated copper;

[0104] S3, such as Figure 5c As shown, the third layer of patterned metal circuit layer 113 an...

Embodiment 3

[0115] Such as Image 6 As shown, based on the LCP packaging substrate described in Embodiment 1-2, this embodiment provides a multi-chip system-in-package structure 61, including: the LCP packaging substrate 1 described in Embodiment 1-2, and BGA solder balls 2. Chip 3, metal frame 5 and metal cover 6;

[0116] The BGA solder balls 2 are soldered to the bottom surface of the LCP packaging substrate 1, and serve as the external secondary cascade I / O interface of the multi-chip system-in-package structure 61;

[0117] Metal partitions 51 are distributed in the metal enclosure 5; the metal enclosure 5 and the metal partitions 51 are welded to the upper surface of the LCP packaging substrate 1, and the metal cover 6 is welded to the metal enclosure 5 and the metal partitions 51, between the LCP packaging substrate 1 and the metal cover plate 6, a plurality of cavity structures 7 with airtight sealing performance and electromagnetic shielding performance are formed through the me...

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Abstract

The invention discloses a six-layer wiring LCP packaging substrate, a manufacturing method and a multi-chip system-in-package structure, and the LCP packaging substrate comprises six graphical metal circuit layers which are distributed from the surface to the bottom surface, wherein the six graphical metal circuit layers sequentially comprises a first graphical metal circuit layer, a second graphical metal circuit layer, a third graphical metal circuit layer, a fourth graphical metal circuit layer, a fifth graphical metal circuit layer and a sixth graphical metal circuit layer; five insulatingdielectric layers which are positioned between the adjacent graphical metal circuit layers; a plurality of blind grooves which are positioned in the insulating medium layer between the first graphical metal circuit layer and the second graphical metal circuit layer, wherein openings of the blind grooves face the first graphical metal circuit layer; and a plurality of blind holes which are positioned between the graphical metal circuit layer and the insulating dielectric layer. The LCP packaging substrate of the airtight packaging structure can meet the system-level packaging requirements of multiple chips, high airtight requirements, high electromagnetic shielding and high reliable interconnection.

Description

technical field [0001] The invention relates to the technical field of integrated circuits and chip packaging, in particular to a six-layer wiring LCP packaging substrate, a manufacturing method and a multi-chip system-level packaging structure, which are used for high-reliability system-level applications for high-frequency applications such as radio frequency, microwave, and millimeter wave. encapsulation. Background technique [0002] With the advancement of semiconductor and integrated circuit technology, the requirements for system integration have been further improved. The current design and manufacture of electronic circuits are moving towards smaller sizes and higher integration densities. Considerable work is carried out in the field of multi-chip packaging. In the advanced packaging form, multiple radio frequency (RF) chips, digital integrated circuit (IC) chips, micro-chip components, etc. are assembled on the packaging substrate through SIP technology, and then ...

Claims

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Application Information

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IPC IPC(8): H01L23/538H01L23/498H01L23/552H01L21/48H01L21/768
CPCH01L23/49894H01L23/49838H01L23/5386H01L23/552H01L23/49816H01L21/4846H01L21/4853H01L21/76895
Inventor 戴广乾徐诺心景飞曾策笪余生龚小林马宁蒋瑶珮林玉敏王栋
Owner SOUTHWEST CHINA RES INST OF ELECTRONICS EQUIP
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