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Covalent grafting of fluorine-free nanoporous low k dielectric films on semiconductor surfaces

A surface covalent, dielectric thin film technology, applied in nanotechnology for materials and surface science, semiconductor/solid-state device manufacturing, nanotechnology, etc., can solve problems such as the inability to achieve low dielectric constant, and achieve thin film thickness. Controllable, controllable composition, prevent strong corrosion effect

Active Publication Date: 2022-07-26
SHANGHAI JIAOTONG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] CN201910087448 provides a method for preparing self-crosslinking organic polymers on semiconductor surfaces; films can be grafted on semiconductor surfaces, but the performance of low dielectric constant cannot be achieved

Method used

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  • Covalent grafting of fluorine-free nanoporous low k dielectric films on semiconductor surfaces
  • Covalent grafting of fluorine-free nanoporous low k dielectric films on semiconductor surfaces
  • Covalent grafting of fluorine-free nanoporous low k dielectric films on semiconductor surfaces

Examples

Experimental program
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Effect test

Embodiment 1

[0046] This embodiment relates to a method for covalently grafting a low k dielectric film on a semiconductor surface based on the diazonium salt technology. The semiconductor substrate may be silicon, germanium, or gallium arsenide (specifically, silicon is selected as the substrate in this embodiment). The implementation steps are as follows:

[0047] Step (1): at a temperature of 20°C, use acetone, alcohol and deionized water to perform ultrasonic cleaning on the semiconductor substrate in turn, and each cleaning time is 5min;

[0048] Step (2): at a temperature of 20° C., place the cleaned semiconductor substrate in a 3v% HF solution, and the soaking time is 1min;

[0049] Step (3): at a temperature of 20°C, directly immerse the corroded semiconductor surface into the prepared chemical solution ① for surface passivation, and the immersion time is 30s, so that the semiconductor surface is converted into a passivation layer surface, thereby preventing the semiconductor The ...

Embodiment 2

[0058] The present embodiment relates to a method for covalently grafting a low k dielectric film on a semiconductor surface based on the diazonium salt technology, the semiconductor substrate is silicon, and the specific implementation steps are as follows:

[0059] Step (1): at a temperature of 20°C, use acetone, alcohol and deionized water to perform ultrasonic cleaning on the semiconductor substrate in turn, and each cleaning time is 5min;

[0060] Step (2): under the condition of temperature of 20°C, the cleaned semiconductor substrate is placed in a 0.5v% HF solution, and the soaking time is 10min;

[0061] Step (3): at a temperature of 20°C, directly immerse the corroded semiconductor surface in the prepared chemical solution ① for surface passivation, and the immersion time is 30s, so that the semiconductor surface is converted into a passivation layer surface, thereby preventing the semiconductor The surface is oxidized in the next reaction;

[0062] The configuratio...

Embodiment 3

[0067] The present embodiment relates to a method for covalently grafting a low k dielectric film on a semiconductor surface based on the diazonium salt technology, the semiconductor substrate is silicon, and the specific implementation steps are as follows:

[0068] Step (1): at a temperature of 20°C, use acetone, alcohol and deionized water to perform ultrasonic cleaning on the semiconductor substrate in turn, and each cleaning time is 5min;

[0069] Step (2): under the condition of temperature of 20 ° C, the cleaned semiconductor substrate is placed in the HF solution of 5% volume fraction, and the soaking time is 1 min;

[0070] Step (3): at a temperature of 20°C, directly immerse the corroded semiconductor surface in the configured chemical solution ① for surface passivation, and the immersion time is 1min, so that the semiconductor surface is converted into a passivation layer surface, thereby preventing H The passivated semiconductor surface is oxidized in the next reac...

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Abstract

The invention discloses a method for covalently grafting a fluorine-free nano-hole low k dielectric film on a semiconductor surface. The method comprises the following steps: chemically grafting a passivation layer on the semiconductor surface by using a diazonium salt technology in an atmospheric environment. The passivation layer is composed of: The organic polymer of diazonium salt, the thickness of the passivation layer is controllable, the purpose is to prevent the surface of Si-H from being oxidized and act as an intermediary layer for the grafted low k film; in the atmospheric environment, the diazonium salt technology is used to electrograft on the surface. The low k layer of the POSS cage structure. The dielectric constant value of the thin film prepared by this method is 2.1-2.2, which has a significantly lower dielectric constant compared with previous studies. This method can be carried out completely in the atmospheric environment, without the protection of inert gas atmosphere, and can graft any soluble vinyl monomer, which can prevent the corrosion of F ions to the monomer and the destruction of some covalent bonds. The dielectric film obtained by the invention has excellent comprehensive properties such as dielectric properties and hardness.

Description

technical field [0001] The invention relates to the technical field of semiconductor surface covalent grafting organic insulating films and low k materials, relates to a method for covalently grafting low dielectric constant (low k) dielectric films on semiconductor surfaces, and in particular relates to a semiconductor surface covalent grafting method A method for grafting fluorine-free nanoscale porous low k dielectric films. Background technique [0002] As a key technology in the production of ultralarge scale integration (ULSI), multi-layer interconnection technology has made great progress in recent years. As the size of electronic devices in VLSI continues to be miniaturized, the propagation delay caused by interconnects increases rapidly. In order to meet the needs of high-speed information transmission in 6G communication in the future, it is urgent to reduce the resistance-capacitance (RC) delay between interconnect layers, and low-k insulating materials are urgen...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/02B82Y30/00
CPCH01L21/02203H01L21/02118H01L21/02282B82Y30/00
Inventor 曹亮亮吴蕴雯李明
Owner SHANGHAI JIAOTONG UNIV
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