Converged network lane line detection method based on attention mechanism and terminal equipment
A technology for lane line detection and fusion network, which is applied in the field of fusion network lane line detection method and terminal equipment based on attention mechanism
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Embodiment 2
[0140] Embodiment 2 of the present invention discloses a fusion network lane line detection system based on attention mechanism, including:
[0141] The data collection module is used for synchronous collection of natural images and point cloud data of the road surface;
[0142] The lane monitoring module is used to input the natural image and point cloud data into the pre-established and trained fusion network, and output the lane detection result; the fusion network adopts adding timing frames and attention mechanism to fuse the point cloud data and natural image information deal with.
Embodiment 3
[0144] Such as Figure 13 As shown, a terminal device provided by Embodiment 3 of the present invention includes: at least one processor 301 , a memory 302 , at least one network interface 303 and a user interface 304 . The various components are coupled together via a bus system 305 . It can be understood that the bus system 305 is used to realize connection and communication between these components. In addition to the data bus, the bus system 305 also includes a power bus, a control bus and a status signal bus. However, for clarity of illustration, the various buses are labeled as bus system 305 in the figure.
[0145] Wherein, the user interface 304 may include a display, a keyboard or a pointing device (for example, a mouse, a track ball (track ball), a touch panel or a touch screen, and the like.
[0146] It can be understood that the memory 302 in the embodiment of the present disclosure may be a volatile memory or a non-volatile memory, or may include both volatile ...
Embodiment 1
[0151] The method in Embodiment 1 may be applied to the processor 301 or implemented by the processor 301 . The processor 301 may be an integrated circuit chip with signal processing capability. In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in the processor 301 or instructions in the form of software. The above-mentioned processor 301 may be a general-purpose processor, a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable GateArray, FPGA) or other programmable Logic devices, discrete gate or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in Embodiment 1 can be realized or executed. A general-purpose processor may be a microprocessor, or the processor may be any conventional processor, or the...
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