Polishing pad, polishing equipment and polishing method of silicon wafer

Abstract

The invention provides a polishing pad, polishing equipment and a polishing method of a silicon wafer. The polishing pad comprises a polishing surface in contact with the silicon wafer, the polishingsurface is provided with at least one groove, the grooving positions of the grooves enable the edge of the silicon wafer to be at least partially suspended above the grooves when the silicon wafer ispolished. According to the polishing pad, the polishing equipment and the polishing method of the silicon wafer, only the polishing rate of the edge position of the silicon wafer is reduced under thecondition that the polishing rate of the whole wafer is kept basically unchanged, so that the flatness of the edge thickness of the silicon wafer is improved, and the product yield is increased.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a polishing pad, polishing equipment and a method for polishing a silicon wafer. Background technique [0002] With the continuous development of IC (Integrated Circuit) technology, the semiconductor industry has higher and higher requirements for silicon wafers. In order to prevent out-of-focus during exposure, the requirements for the flatness of silicon wafers are also becoming more and more stringent. [0003] The surface polishing of silicon wafers often requires two polishing steps: double side polishing (DSP, double side polish) and front final polishing (FP, final polish). Double-side polishing is used to grind the front and back sides of the wafer, and the desired wafer shape can be achieved through the control of the polishing disc, while the final polishing only polishes the front side of the silicon wafer. [0004] For the final polishing process of silicon wa...

AI Technical Summary

Problems solved by technology

During the polishing process, the polishing liquid is easy to accumulate on the edge of the silicon wafer, resulting in a thinner edge of the silicon wafer

With the existing conventional process equipment and process capabilities, it is often impossible to implement accurate adjustment at the edge of the silicon wafer at a position of about 145mm to 149mm, especially when the polishing rate of the entire wafer is kept basically unchanged, only the edge position of the silicon wafer is reduced. The polishing rate is more difficult to achieve by adjusting the existing process parameters

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