FPGA version loading method and device and storage medium

Abstract

The invention provides an FPGA version loading method and device and a storage medium. The method comprises the steps: configuring a first pin and a second pin on a specified chip connected with a central processing unit into a mode that an output signal is valid after a kernel system is started; adjusting the output levels of the first pin and the second pin; and controlling a third pin and a fourth pin respectively corresponding to the first pin and the second pin on the FPGA chip equipment to work, after the FPGA basic version is loaded, enabling a high-speed serial computer extension bus standard PCIE link between the FPGA chip device and the central processing unit to be in a connected state; after the PCIE link is in a connected state, detecting whether the FPGA chip equipment existsin the kernel system or not, and obtaining a detection result; and at least executing a scanning operation of re-scanning the FPGA chip device according to the detection result. According to the method and the device, the stability of loading the FPGA version through the PCIE bus is improved.

Description

technical field [0001] The present disclosure relates to the computer field, and in particular to a method and device for loading an FPGA version, and a storage medium. Background technique [0002] At present, FPGA (Field Programmable Gate Array, Field Programmable Gate Array) chips are more and more widely used in high-end network security equipment, and can replace switching chips and Phy (Physical, physical layer) chips to realize the sending and receiving of network messages on the panel port . FPGA needs to have a version configuration file adapted to the FPGA chip device to start working, and the version loading method becomes the first step to make the chip work. [0003] After the device is powered on, the hardware resets the FPGA, the BIOS (Basic Input Output System, basic input and output system) scans the entire PCIE (Peripheral Component Interconnect Express, high-speed serial computer expansion bus standard), initializes and configures the PCIE device After t...

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Problems solved by technology

[0004] However, after the hardware is powered on, due to the uncontrollable hardware timing, there may be a time when the hardware reset pin is pulled up after the BIOS scans the PCIE device globally. In this case, the BIOS will not scan the FPGA chip device, causing the kernel to start Afterwards, the FPGA and PCIE bus link status is disconnected, and the FPGA chip device cannot be loaded.

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