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Two-dimensional convolution implementation method and device

A technology of two-dimensional convolution and implementation method, applied in physical implementation, neural architecture, biological neural network model, etc., can solve the problems of complex control and complex two-dimensional convolution addressing, so as to improve computing efficiency and reduce addressing. Difficulty, Simplified Routing Complexity, and Effects of Controlling Complexity

Pending Publication Date: 2020-05-26
YUSUR TECH CO LTD
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Problems solved by technology

[0004] The technical problem to be solved by the present invention is to provide a two-dimensional convolution implementation method and device for the problems of complex addressing and complex control of two-dimensional convolution in the prior art

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  • Two-dimensional convolution implementation method and device

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[0037] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with the embodiments and accompanying drawings. Here, the exemplary embodiments and descriptions of the present invention are used to explain the present invention, but not to limit the present invention.

[0038] Here, it should also be noted that, in order to avoid obscuring the present invention due to unnecessary details, only the structures and / or processing steps closely related to the solution according to the present invention are shown in the drawings, and the related Other details are not relevant to the invention.

[0039] It should be emphasized that the term "comprises / comprises / has" when used herein refers to the presence of a feature, element, step or component, but does not exclude the presence or addition of one or more other features, elements, steps or components.

[0040] Here...

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Abstract

The invention provides a two-dimensional convolution implementation method and device. The method comprises the steps: one-dimension processing of two-dimensional input data, wherein two-dimensional input data is expanded into one-dimensional data according to a set dimension; convolution core decomposition, wherein the two-dimensional convolution core is decomposed into independent rows or columns according to the expansion mode of the two-dimensional input data; sub-result calculation, wherein the one-dimensional data is subjected to one-dimensional convolution operation respectively with the decomposed convolution core to correspondingly obtain a plurality of one-dimensional sub-result sequences; and sub-result merging, wherein all corresponding data in the multiple one-dimensional sub-result sequences are merged to obtain and output a final two-dimensional convolution calculation result. The invention further provides a two-dimensional convolution implementation device. According to the method and the device, all two-dimensional data can be converted into one-dimensional data, and two-dimensional convolution operation can be completed through one-dimensional convolution operation, so that the control complexity and the on-chip data routing difficulty are greatly simplified.

Description

technical field [0001] The invention relates to data and database processing, in particular to a two-dimensional convolution realization method and device for sorting data processing. Background technique [0002] Two-dimensional convolution is one of the core operations in many scientific calculations, accounting for most of the calculations in the entire application, such as the calculation between the input feature image and the two-dimensional convolution kernel in each layer of the convolutional neural network, Occupies more than 90% of the calculations in the entire network model. Therefore, improving the computational efficiency of two-dimensional convolution is the key to the optimization of many core scientific calculations. [0003] In order to accelerate the computational efficiency of two-dimensional convolution, more and more dedicated computing architectures have been proposed. This type of computing architecture is mostly designed according to the characteris...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06N3/04G06N3/063
CPCG06N3/063G06N3/045
Inventor 鄢贵海卢文岩
Owner YUSUR TECH CO LTD
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