Magnetic random access memory with error correction and compression circuit

Abstract

The invention provides a magnetic random access memory with an error correction and compression circuit. The magnetic random access memory comprises a memory cell array, an error detection and correction circuit, a compression and decompression circuit, a control circuit, a status bit cache and a data cache, the reading operation steps of the chip are as follows: obtaining first compressed data inthe memory cell array, processing the first compressed data through the error detection and correction circuit, decompressing the processed first compressed data through the compression and decompression circuit to obtain first data, and outputting the first data; and the chip performs the following writing operation steps: compressing second data to be written through the compression and decompression circuit to obtain second compressed data, processing the second compressed data through the error detection and correction circuit, and writing the processed second compressed data into the memory cell array.

Description

technical field [0001] The invention relates to a storage device, in particular to a magnetic random access memory with error correction and compression circuits, and belongs to the technical field of semiconductor chips. Background technique [0002] MRAM is a new memory and storage technology that can be read and written as fast as SRAM / DRAM, and can permanently retain data after power failure like Flash memory. Its economy is quite good, and the silicon area occupied per unit capacity has a great advantage over SRAM, and also has advantages over NOR Flash, which is often used in such chips, and has greater advantages than embedded NOR Flash. Its performance is also quite good, the read and write latency is close to the best SRAM, and the power consumption is the best among various memory and storage technologies. Moreover, unlike DRAM and Flash, MRAM is not compatible with standard CMOS semiconductor processes. MRAM can be integrated into a chip with logic circuits. [...

AI Technical Summary

Problems solved by technology

[0009] In view of the above-mentioned defects of the prior art, the technical problem to be solved by the present invention is: the error correction circuit, compression and decompression circuit in the prior art have long read and write delays and low performance

Images