A magnetic random access memory using arched word lines

Abstract

The present invention provides a magnetic random access memory using arched word lines. An array is formed by a cell structure, and the cell structure at least includes an active region carrying layer, an arched word line segment, a first contact column, a second contact column, and a third contact column; The first contact column, the third contact column, and the second contact column are sequentially arranged on the active region carrying layer; the arched word line segment passes through the area between the first contact column, the second contact column and the third contact column, so as to The first contact stud and the second contact stud are located on one side of the arched word line segment, the third contact stud is located on the other side of the arched word line segment, and there is an oxide layer under the arched word line segment. The beneficial effects of the present invention: (1) the design of the peripheral circuit is simple; (2) only two columns share the source line, and the speed is fast; (3) in the active area of ​​the same area, it can withstand greater current and provide faster Speed; (4) Using one less layer of metal reduces the cost, reduces the mutual inductance capacitance, and also helps to increase the speed.

Description

technical field [0001] The invention relates to a storage device, in particular to a magnetic random access memory using arcuate word lines, belonging to the technical field of integrated circuit memory chips. Background technique [0002] MRAM is a new memory and storage technology that can be read and written as fast and random as SRAM / DRAM, and can also retain data permanently after a power failure like Flash. Its economy is quite good, and the silicon area occupied by the unit capacity has a great advantage over SRAM, and it also has an advantage over NOR Flash, which is often used in such chips, and has a greater advantage than embedded NOR Flash. Its performance is also quite good, the read and write latency is close to the best SRAM, and the power consumption is the best in various memory and storage technologies. Moreover, unlike DRAM and Flash, MRAM is not compatible with standard CMOS semiconductor processes. MRAM can be integrated with logic circuits into one chi...

AI Technical Summary

Problems solved by technology

from Figure 14 It can be seen that the source lines 130 and 132 still occupy some space between the active regions of the two columns, reducing the density

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