Reconfigurable field effect transistor with structure of asymmetric sidewalls and vertically stacked channels

Abstract

The invention discloses a reconfigurable field effect transistor with a structure of asymmetric sidewalls and vertically stacked channels. The transistor comprises multiple vertically stacked channels, gate oxides wrapping the outer side of the channels, source and drain electrodes which are arranged on the two ends of the channels, a source sidewall arranged at the right side of the source electrode, a source sidewall arranged at the left side of the drain electrode, a control gate arranged at the right side of the source sidewall, a polar gate arranged at the left side of the drain sidewall,a gate isolation arranged between the control gate and the polar gate and a substrate arranged at the bottom. The transistor is characterized in that the source sidewall and the drain sidewall use different materials, and the length of the source sidewall is less than or equal to the length of the drain sidewall; and the channels are stacked at least twice along the direction perpendicular to thesubstrate. The higher current density can be obtained on the same area so that the effect of reducing the delay of the combinational logic and improving the current driving ability can be achieved.

Description

technical field [0001] The invention belongs to the digital logic and storage device in the complementary metal oxide semiconductor (CMOS) very large integrated circuit (VLSI), and specifically relates to a reconfigurable field effect transistor with an asymmetric side wall and a vertically stacked channel structure. Background technique [0002] The continuous development of the semiconductor industry is closely related to the reduction of the size of semiconductor devices. The reduction of device size can improve the turn-on current, characteristic frequency and energy efficiency of the device, reduce the delay and area of ​​the device, thereby generating a steady stream of value, and promote the continuous development of the information industry. before development. However, the reduction in the size of semiconductor devices will eventually reach its physical limit. In order to continue the integrated circuit development cycle of Moore's Law, which doubles the performance...

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Problems solved by technology

[0005] The purpose of the present invention is to solve the problem of low on-state drive current and high process development cost of existing general symmetric structure reconfigurable transistors. On the basis of the current mainstream CMOS manufacturing process, a reconfigurable field-effect transistor with asymmetrical sidewalls and vertically stacked channels is proposed, which can realize the leakage current and symmetry of both N-type and P-type polarities of the device. Under the same order of magnitude of the leakage current of the reconfigurable transistor, the N-type and P-type open-state driving current of the device can be increased, the current switching ratio of the device can be improved, the delay time of the logic gate of the integrated circuit can be reduced, and the characteristic frequency of the transistor can be improved. , and all process steps are compatible with the current CMOS large-scale process

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