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FPGA parallel acceleration system based on CNN image quality enhancement algorithm

A technology that enhances algorithms and accelerates systems, and is used in concurrent instruction execution, computing, neural learning methods, etc. to reduce power consumption, achieve computing efficiency, and meet the needs of video and image applications.

Pending Publication Date: 2019-08-02
SOUTHEAST UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] The technical problem to be solved by the present invention is to provide a CNN-based image quality enhancement algorithm FPGA parallel acceleration system for convolutional neural network storage-intensive and computationally intensive features and real-time requirements for post-processing of video images, using FPGA hardware The accelerated method implements the image quality enhancement algorithm based on CNN. By adopting parallel optimization and pipeline optimization methods, the processing speed of the image quality enhancement can be significantly improved compared with CPU calculation, and single-frame image processing can be guaranteed at a lower operating frequency. The speed is maintained at the millisecond (ms) level, and the power consumption is greatly reduced, which can meet the real-time high-speed video image application requirements in the actual embedded scene

Method used

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  • FPGA parallel acceleration system based on CNN image quality enhancement algorithm
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Embodiment Construction

[0035] Embodiments of the present invention will be described below in conjunction with the accompanying drawings.

[0036] Such asfigure 1 As shown, the present invention designs a kind of FPGA parallel acceleration system based on the picture quality enhancement algorithm of CNN, mainly comprises: CPU, DMA controller, bus module, accelerator IP core module, on-chip memory BRAM, off-chip memory SDRAM. The main design considerations for each module are as follows:

[0037] The central processing unit is mainly used to control the system operation process in this system, including controlling the start and stop of the accelerator, configuring the accelerator, processing accelerator interrupts, and controlling the DMA to complete data transfer.

[0038] The accelerator IP core module, the core computing system of the present invention, is designed on the basis of the third point above, and is mainly composed of LUT and DSP resources inside the FPGA. During calculation, each cal...

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Abstract

The invention discloses an FPGA parallel acceleration system based on a CNN image quality enhancement algorithm. The FPGA parallel acceleration system comprises a central processing unit, a DMA controller, a bus module, an accelerator IP core module, an on-chip memory BRAM and an off-chip memory SDRAM. The central processing unit performs fixed-point quantification on the weight data of the trained convolutional neural network model to obtain quantified weight data and stores the quantified weight data in the off-chip SRDAM; the DMA controller carries the weight data pre-stored in the off-chipSDRAM and the video image data to be processed to an on-chip memory BRAM for block storage; the accelerator IP core module adopts multiplier parallel optimization and dimension conversion and streamline line line caching and shared ping design optimization operation, the central processing unit starts the accelerator IP core module and obtains data from the BRAM to carry out forward calculation of a network, and a picture obtained through calculation is carried to the off-chip SDRAM. According to the invention, the power consumption is greatly reduced, the balance of FPGA resource utilizationand operation efficiency is realized, and the video image application requirement in an actual embedded scene can be met.

Description

technical field [0001] The invention relates to an FPGA parallel acceleration system based on a CNN-based image quality enhancement algorithm, and belongs to the technical field of digital integrated circuits. Background technique [0002] With the rapid development of computer, Internet and multimedia technology, digital image and video technology have been widely used in real life. In all these applications, including video conferencing, digital cameras, mobile video, image or video network transmission, etc., a very efficient data compression method is required to compress a large amount of visual information into a limited physical bandwidth, while ensuring The data reconstructed at the data receiving end retains considerable quality. Such a requirement is a huge challenge to the existing compression coding methods and standards, because the image or video will inevitably degrade the image quality under the condition of high compression ratio, such as ringing, blurring,...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06T1/20G06F9/38G06N3/04G06N3/08
CPCG06T1/20G06F9/3867G06F9/382G06N3/08G06N3/044G06N3/045
Inventor 李冰刘彬峰张林王亚洲刘勇董乾王刚赵霞
Owner SOUTHEAST UNIV
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