Convolutional neural network IP core based on FPGA

Abstract

The invention discloses a convolutional neural network IP core based on FPGA, and aims to realize operation acceleration of a convolutional neural network on an FPGA. According to the basic model of the convolutional neural network, the specific architecture of the convolutional neural network comprises a convolution operation IP core, a pooling operation IP core, a full connection operation IP core, a bubbling method convolution layer, a bubbling method pooling layer, a full connection layer, a feature map storage module and a parameter storage module. The IP cores support construction of convolutional neural networks of different scales, and the IP cores of different types and numbers are instantiated according to the required network model. Different neural network layers are constructed by instantiating the IP core, and the parallelism of the FPGA is fully utilized to realize the operation acceleration of the convolutional neural network; and designing an IP core through a VerilogHDL language to realize transplantation of different FPGAs. The operation speed and efficiency of the convolutional neural network are greatly improved, and the processing power consumption of the convolutional neural network is reduced.

Description

technical field [0001] The invention relates to the field of convolutional neural network hardware acceleration, in particular to the design of an FPGA-based convolutional neural network IP core. Background technique [0002] With the rise and improvement of machine learning, deep learning and artificial intelligence in recent years, Artificial Neural Network (ANN) continues to develop. world attention. The early artificial neural network was similar to the bionic nervous system structure, and a computing structure that simulated the neuron structure of the human brain was proposed in the middle of the 20th century. The dendrite branch of the human neuron structure is simulated as multiple input data, and the axon is simulated as a single output data. Through certain data transformation, that is, linear weighting, the axon's nerve signal output is realized. [0003] Manually setting thresholds and various linearly weighted weights is cumbersome and may not achieve the best...

AI Technical Summary

Problems solved by technology

Moreover, FPGA products are launched quickly. Today, with the ever-changing neural network structure, they can be put into the market quickly, avoiding the poor flexibility of ASIC chips that can only be designed for specific algorithms.

[0008] The existing FPGA acceleration schemes are roughly as follows: 1. Adopt low-power high-performance accelerator design, and improve memory access bandwidth by stacking a small number of processing units (Processing Unit, PE), but there are fewer pipelines resulting in lower data throughput , even there is a redundant pipeline design in the convolution process

2. Use smaller processing units (ProcessingElement, PE) to build convolution kernels of different sizes to avoid the problem of computing bottlenecks, but lead to long convolution calculation delays and limited peak computing performance

3. Design an accelerator for frequency domain processing, use variable-size OaA convolution kernels to reduce the number of convolutions and improve the versatility of convolution kernels at different levels, but its OaA is composed of fixed-size FFTs, resulting in convolution processing requiring 0 Padding the FFT edges, and tiling the convolution kernel leads to a long convolution delay

On the other hand, hardware design, modification and debugging are a threshold for software engineers and algorithm engineers who are not familiar with hardware, which may increase costs and extend working hours for enterprises

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