Parallel bus serial interconnection expansion method with error correction and automatic response mechanisms

Abstract

The invention discloses a parallel bus serial interconnection expansion method with error correction and automatic response mechanisms. A CPU and a plurality of slave FPGAs are connected through a master FPGA, and the master FPGA internally comprises a parallel bus interface and a plurality of master serial interface control circuits, wherein the parallel bus interface and the master serial interface control circuits are connected with the CPU. Each slave FPGA internally comprises a slave serial interface control circuit which is connected with the master FPGA in a serial manner and is interconnected with the slave FPGA internal circuit in a parallel bus interface manner; cPU pass register, the memory mapping mode controls the work of the main serial interface control circuit; an indirectstorage access command is sent to a slave serial interface circuit in a certain FPGA in an existing or user-defined serial communication mode in a burst short packet command mode. wherein the commandcomprises a read / write operation type, an operation address, read / write operation data and a check code, receiving the operation command from a serial interface control circuit in the FPGA, convertingthe operation command into a bus interface and an operation time sequence which are the same as those in the main FPGA, and performing read / write operation on an internal storage space. According tothe invention, high-efficiency, reliable, simple and strong-interactivity data communication between the processor and the plurality of FPGAs can be provided, and the universality is high.

Description

technical field [0001] The invention relates to the technical field of electronic circuits, and is mainly used for communication between a processor (CPU) and multiple FPGAs, in particular to a parallel bus serial interconnection expansion with error correction and automatic response mechanism realized by hardware description language Method, using this technology can realize flexible, reliable, simple, strong interactive and easy to expand multi-FPGA communication mode. Background technique [0002] In many applications, the processor (CPU) needs to communicate with multiple FPGAs on a single circuit board at the same time, or communicate with FPGAs distributed on different circuit boards through the backplane to work on the circuits in the FPGA. configuration, status queries, and low-speed data transfers. [0003] The traditional method needs to use at least one level of bidirectional bus driver circuit. Each FPGA needs to use a parallel bus interface circuit. It uses reg...

AI Technical Summary

Problems solved by technology

The advantage of this method is that the CPU can directly address each FPGA, and the operation mode is simple, but this method occupies a large number of FPGA pins, which will cause complex board-level wiring and backplane wiring, and affect signal integrity and bus drivers. It also has high requirements, lacks an error control mechanism, and the size of the available memory mapping space is limited by the width of the address lines in the bus

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