Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

An Extended Method of Parallel Bus Serial Interconnection with Error Correction and Automatic Response Mechanism

A technology of automatic response and extension method, which is applied in the fields of climate sustainability, instrumentation, electrical digital data processing, etc., and can solve the problem of high signal integrity and bus drive requirements, complex board-level wiring and backplane wiring, FPGA pin Large quantity and other problems, to achieve the effect of easy guarantee of signal integrity, improvement of reliability and reduction of complexity

Active Publication Date: 2022-05-24
ARMY ENG UNIV OF PLA
View PDF10 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The advantage of this method is that the CPU can directly address each FPGA, and the operation mode is simple, but this method occupies a large number of FPGA pins, which will cause complex board-level wiring and backplane wiring, and affect signal integrity and bus drivers. It also has high requirements, lacks an error control mechanism, and the size of the available memory mapping space is limited by the width of the address lines in the bus

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • An Extended Method of Parallel Bus Serial Interconnection with Error Correction and Automatic Response Mechanism
  • An Extended Method of Parallel Bus Serial Interconnection with Error Correction and Automatic Response Mechanism
  • An Extended Method of Parallel Bus Serial Interconnection with Error Correction and Automatic Response Mechanism

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0010] The present invention expands the parallel bus in the way of serial communication, so that the CPU can manage a large number of FPGAs in the way of indirect storage access and can save the memory mapping space; the common serial communication mode (such as Asynchronous serial mode) to reduce the complexity of board-level wiring and backplane wiring; the communication between the master and slave serial bus interface circuits has its own verification and response mechanism, which can detect operation errors in time. This communication method is flexible, reliable, simple, interactive and easy to expand

[0011] The present invention will be further described below in conjunction with the accompanying drawings.

[0012] combine figure 1 , The parallel bus serial interconnection expansion method with error correction and automatic response mechanism of the present invention includes a CPU, a master FPGA and a slave FPGA, and the system connects the CPU and multiple slave ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a parallel bus serial interconnection expansion method with an error correction and automatic response mechanism. The CPU and multiple slave FPGAs are connected through a master FPGA. The master FPGA includes a parallel bus interface interconnected with the CPU and multiple master serial interface control circuits; each slave FPGA includes a slave serial interface control circuit inside. It is interconnected with the main FPGA in a serial manner, and interconnected with the internal circuit of the slave FPGA in a parallel bus interface; the CPU controls the work of the main serial interface control circuit through registers and memory mapping, and sends a burst command to a certain The slave serial interface circuit in the FPGA sends indirect storage access commands in the existing or custom serial communication mode. The commands include read / write operation type, operation address, read / write operation data and check code, and the slave serial interface circuit in the FPGA The serial interface control circuit receives the operation command, converts it into the same bus interface and operation sequence as the main FPGA, and performs read and write operations on the internal storage space. The invention can provide efficient, reliable, simple and strong interactive data communication between the processor and multiple FPGAs, and has high versatility.

Description

technical field [0001] The invention relates to the technical field of electronic circuits, and is mainly used for communication between a processor (CPU) and multiple FPGAs, in particular to a parallel bus serial interconnection expansion with error correction and automatic response mechanism realized by hardware description language Method, using this technology can realize a flexible, reliable, simple, highly interactive and easy-to-expand multi-FPGA communication mode. Background technique [0002] In many applications, a processor (CPU) is required to communicate with multiple FPGAs on a single circuit board at the same time, or communicate with FPGAs distributed on different circuit boards through the backplane to work on the circuits in the FPGA Configuration, status query and low speed data transfer. [0003] The traditional method needs to use at least 1-level bidirectional bus driver circuit. In each FPGA, a parallel bus interface circuit needs to be used, and reg...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/362G06F13/38
CPCG06F13/362G06F13/385G06F2213/0004G06F2213/0002Y02D10/00
Inventor 乔庐峰陈庆华钱鹏飞武东明杨健邹仕祥
Owner ARMY ENG UNIV OF PLA
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products