An apparatus and method for performing a forward operation of a convolution neural network

Abstract

The invention provides an apparatus for executing a convolutional neural network, wherein the apparatus comprises an instruction storage unit, a controller unit, a data access unit, an interconnectionmodule, a master operation module, and a plurality of slave operation modules. The forward operation of one or more artificial neural network convolution layers can be realized by using the device. For each layer, the input neuron vector is firstly selected according to the convolution window, and then the convolution operation is performed with the convolution kernel to calculate the intermediate result of the layer, and then the intermediate result is biased and activated to obtain the output data. The output data is used as input data for the next layer.

Description

technical field [0001] The present invention generally relates to artificial neural networks, and in particular to a device and method for performing forward operations of convolutional neural networks. Background technique [0002] Convolutional neural network is an efficient recognition algorithm widely used in pattern recognition, image processing and other fields in recent years. It has the characteristics of simple structure, few training parameters and strong adaptability, translation, rotation and scaling. Since the feature detection layer of CNN / DNN learns through training data, when using CNN / DNN, it avoids explicit feature extraction and learns implicitly from training data; The weights of the cells are the same, so the network can learn in parallel, which is also a big advantage of the convolutional network over the network of neurons connected to each other. [0003] In existing computer field applications, applications related to convolution operations are very...

AI Technical Summary

Problems solved by technology

[0007] The purpose of the present invention is to provide a device supporting convolutional neural network, which solves the problems existing in the prior art such as limited inter-chip communication, insufficient on-chip cache, etc.

Images