Semiconductor structure

Abstract

The invention relates to a semiconductor structure comprising a substrate, a memory stacked structure formed on the surface of the substrate, a grid line spacing slot penetrating the memory stacked structure to the surface of the substrate, and a semiconductor layer filling the grid line spacing slot. The semiconductor layer is doped with doping atoms for reducing the crystal particle size. The semiconductor layer formed based on the semiconductor structure has small crystal particles; and the performance of the semiconductor structure can be improved.

Description

technical field [0001] The invention relates to the field of semiconductor production and preparation, in particular to a semiconductor structure. Background technique [0002] In recent years, the development of flash memory (Flash Memory) is particularly rapid. The main feature of flash memory is that it can keep stored information for a long time without power on, and has the advantages of high integration, fast access speed, easy erasing and rewriting, etc. Has been widely used. In order to further increase the bit density (Bit Density) of the flash memory while reducing the bit cost (Bit Cost), three-dimensional flash memory (3D NAND) technology has been developed rapidly. [0003] In the process of forming a 3D NAND memory, it is necessary to form a stacked structure consisting of a sacrificial layer and an insulating layer on the surface of the substrate, then etch the stacked structure to form a gate line spacer, and then fill the gate line spacer with a semiconduc...

AI Technical Summary

Problems solved by technology

The polysilicon layer has less strain after subsequent high-temperature annealing, but usually there is a gap with the inner wall surface of the gate line spacer, which cannot be completely attached to the surface of the gate line spacer, and voids are prone to appear inside, which affects the final formed memory performance; the amorphous semiconductor material layer can fill the gate line spacer, and there is no gap between the surface of the gate line spacer and no void inside, but crystallization will occur after subsequent high-temperature annealing, and a large stress will be applied to the substrate , which leads to problems such as substrate warpage, which affects the performance of the final memory

[0005] Therefore, the performance of the memory formed by the prior art needs to be further improved

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