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Trench gate power MOS transistor containing semi-insulating region and preparation method

A MOS transistor and semi-insulating technology, applied in the field of trench gate power MOS transistors and their fabrication, can solve problems such as low avalanche resistance, and achieve the effects of improving breakdown voltage, ensuring threshold voltage, and improving avalanche resistance and robustness.

Active Publication Date: 2018-10-19
ANHUI UNIVERSITY OF TECHNOLOGY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] Aiming at the problem of low avalanche tolerance of trench gate power MOS transistors in the prior art, the present invention provides a trench gate power MOS transistor containing a semi-insulating region and a preparation method thereof

Method used

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  • Trench gate power MOS transistor containing semi-insulating region and preparation method
  • Trench gate power MOS transistor containing semi-insulating region and preparation method
  • Trench gate power MOS transistor containing semi-insulating region and preparation method

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Experimental program
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Effect test

Embodiment 1

[0050] Combine image 3 , 4 A trench gate power MOS transistor with a semi-insulating region of this embodiment includes a source region 21 doped with a second conductivity type, a base region 22 doped with a first conductivity type, and a semi-insulating region 222. The second conductivity type The doped source region 21 is located above the first conductive type doped base region 22 and the semi-insulated region 222 arranged side by side, and the bottom of the semi-insulated region 222 is in contact with the second conductive type doped drift layer 12.

[0051] The existence of the semi-insulating region 222 reduces the area where parasitic BJTs exist, that is, reduces the number of parasitic BJTs, but there are a small amount of parasitic BJTs under the channel region, but the number of parasitic BJTs is greatly reduced, thereby reducing Under UIS conditions, the current in the MOSFET limits the increase in temperature. The avalanche breakdown time of the MOSFET is increased fr...

Embodiment 2

[0056] Combine image 3 , 4 , The trench gate power MOS transistor with semi-insulating region of this embodiment is further improved on the basis of embodiment 1. The width of the source region 21 doped with the second conductivity type is the same as the base region doped with the first conductivity type. The sum of the widths of 22 and the semi-insulating region 222 is equal.

[0057] Precisely control the effective width of the conductive channel formed by the doped base region 22 of the first conductivity type, without changing due to the introduction of the semi-insulating region 222, ensuring the threshold voltage, on-resistance, and transconductance of the trench gate power MOS transistor , Output characteristics and other parameters do not change due to the introduction of the semi-insulated region 222. While not affecting the channel region of the trench gate power MOS transistor, it can not only improve the avalanche tolerance and robustness of the trench gate power MO...

Embodiment 3

[0059] Combine image 3 , 4 In this embodiment, a trench gate power MOS transistor with a semi-insulating region is further improved on the basis of Embodiments 1 and 2. The depth of the base region 22 doped with the first conductivity type is the same as the depth of the semi-insulating region 222 . The width ratio of the first conductive type doped base region 22 to the second conductive type doped source region 21 is 1:1-3. For specific applications, you can choose values ​​such as 1:1; 1:2; 1:3; 1:1.5; 1:2.8.

[0060] Ensure that the effective channel length of the trench-gate power MOS transistor does not change due to the introduction of the semi-insulated region 222, and ensure that the threshold voltage, on-resistance, transconductance, and output characteristics of the trench-gate power MOS transistor are not affected by the semi-insulated region. Introduced and changed. Ensure that the channel carriers are transported smoothly and there is no "overstep", otherwise the...

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Abstract

The invention discloses a trench gate power MOS transistor containing a semi-insulating region and a preparation method, and belongs to the technical field of high voltage power electronics. The trench gate power MOS transistor containing the semi-insulating region comprises a second conduction type-doped source region, and a first conduction type-doped base region and semi-insulating region, thesecond conduction type-doped source region is located above the first conduction type-doped base region and semi-insulating region which are arranged side by side, and the bottom of the semi-insulating region is in contact with a second conduction type semiconductor-doped drifting layer. The semi-insulating region first adopts ion implantation of impurities of the second conduction type to realizecontra-doping to form an electrically neutral layer, and then the semi-insulating region is formed by ion implantation of amphoteric impurity elements. Aiming at the problem of low UIS avalanche tolerance of a trench gate power MOS transistor in the prior art, the UIS avalanche tolerance and robustness of the trench gate power MOS transistor provided by the invention can be remarkably improved, acapability of resisting large current of the trench gate power MOS transistor is improved, the reliability of the trench gate power MOS transistor is improved, and the breakdown voltage of the trenchgate power MOS transistor is appropriately improved.

Description

Technical field [0001] The present invention relates to the technical field of high-voltage power electronics, in particular to a trench gate power MOS transistor containing a semi-insulating region and a preparation method thereof. Background technique [0002] With the continuous improvement of the performance requirements of power conversion devices, higher requirements are put forward for the power MOS transistor devices that undertake the power conversion function. One of them is the high avalanche tolerance in the unclamped inductive load switching process (UIS) , That is, it has high resistance to UIS avalanche breakdown. This is because the energy stored in the inductive load under UIS conditions is required to be released by the power MOS transistor when it is turned off. At this time, the high current stress in the circuit is very high. It is easy to cause device failure, so the level of avalanche breakdown tolerance is one of the important indicators that reflect the p...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/06H01L29/417H01L29/78H01L21/265H01L21/28H01L21/336
CPCH01L29/0607H01L29/0615H01L29/0684H01L29/41741H01L29/66666H01L29/7827H01L21/265H01L21/28H01L29/7813H01L29/7802H01L29/66068H01L29/0653H01L29/167H01L29/1608
Inventor 周郁明王兵
Owner ANHUI UNIVERSITY OF TECHNOLOGY
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