Semiconductor structure and forming method thereof

Abstract

Disclosed are a semiconductor structure and a forming method thereof. The forming method includes the following steps: forming a substrate; forming a gate structure on the substrate; forming source-drain doping regions located in the substrate on two sides of the gate structure; forming a dielectric layer on the substrate exposing from the gate structure, wherein the dielectric layer covers the source-drain doping regions; forming contacting holes passing through the dielectric layer, wherein the bottoms of the contacting holes expose the source-drain doping regions; forming an oxide metal layer on the source-drain doping regions exposing from the contacting holes; and forming plugs in the contacting holes in which the oxide metal layer is formed. The technical scheme of the invention caneffectively inhibit the phenomenon of Fermi level pinning at the interface of the plugs and the source-drain doping regions, thereby benefiting the reduction of the contact resistance between the plugs and the source-drain doping regions, and benefiting the improvement of the performance of the formed semiconductor structure.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] In the integrated circuit manufacturing process, after the semiconductor device structure is formed, it is necessary to connect the semiconductor devices together to form a circuit. With the continuous development of integrated circuit manufacturing technology, people's requirements for the integration and performance of integrated circuits are becoming higher and higher. In order to improve integration and reduce costs, the critical dimensions of components are getting smaller and the circuit density inside integrated circuits is increasing. This development makes it impossible for the surface of the wafer to provide enough area to make the interconnection lines required by conventional circuits. . [0003] In order to meet the requirements of the interconnection line after the crit...

AI Technical Summary

Problems solved by technology

In order to improve integration and reduce costs, the critical dimensions of components are getting smaller and the circuit density inside integrated circuits is increasing. This development makes it impossible for the surface of the wafer to provide enough area to make the interconnection lines required by conventional circuits.

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