Multi-chip stack packaging structure

Abstract

The invention belongs to the technical field of semiconductor chip packaging and is intended to solve the problem that existing chip packaging takes high energy consumption and easily experiences wirefailure. The invention, therefore, provides a multi-chip stack packaging structure, comprising: a substrate having a base and a terrace and including a first chip stack unit and a second chip stack unit, wherein the first and second chip stack units are stacked in staircase manner in opposite directions; bonding wires, including first bonding wires that directly connect the base and chips in thefirst chip stack unit, and second bonding wires that connect the terrace and chips in the second chip stack unit. The terrace is arranged on the base, so that the length of the bonding wires is effectively shortened, the consumption of the wires is reduced, the production cost is reduced, welding time can be shortened, and packaging efficiency is improved; in addition, the shorter bonding wires help effectively improve chip stability and prevent the bonding wires from shaking too much during vibration, causing short circuit and other conditions.

Description

technical field [0001] The invention relates to the technical field of semiconductor chip packaging, in particular to a multi-chip stack packaging structure. Background technique [0002] When an IC (integrated circuit) bare chip is applied, it first needs to be packaged. There are three main functions of encapsulation: ① protect the chip, because the silicon chip itself is relatively fragile, fine dust and water vapor will destroy their functions, and the encapsulation can isolate the chip from the external environment; ② scale up, because the chip itself is very small, through After encapsulation, its size can be enlarged, which is convenient for subsequent PCB (Printed Circuit Board, printed circuit board) board-level system use; ③ for electrical connection, through encapsulation, the chip and the outside world can exchange information stably. [0003] The degree of integration of the package formed after chip packaging is related to the way the chip is packaged. In the...

AI Technical Summary

Problems solved by technology

For cantilever stacking, as the number of stacking layers increases, the number of dielectric layers that need to be added also increases, which reduces the vertical packaging density, thereby reducing the integration of the package; in addition, because the chip size is the same, it must be bonded to the lower chip. The upper chip can only be stacked after the soldering operation of the junction is completed, that is, multiple thermal curing operations are required, which will reduce the packaging efficiency; moreover, the chip on the upper layer needs to be connected to the adjacent chip through the bonding wire, that is, it needs to be bonded on each bond. Multiple welding operations are performed on the bonding point, the process is complicated, the cost is high, and it is easy to cause the bonding point to go off-line

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