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Method for judging Fermi energy level pinning effect of electronic device

A Fermi level, pinning effect technology, applied in the direction of electrical components, semiconductor devices, semiconductor/solid-state device manufacturing, etc., to achieve the effect of simple process and easy operation

Active Publication Date: 2018-07-27
HARBIN INST OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The present invention is to solve the problem that there is no method for determining the Fermi level pinning effect of electronic devices in particle radiation environments

Method used

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  • Method for judging Fermi energy level pinning effect of electronic device
  • Method for judging Fermi energy level pinning effect of electronic device

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Experimental program
Comparison scheme
Effect test

specific Embodiment approach 1

[0023] A method for judging the pinning effect at the Fermi level of an electronic device, comprising the following steps:

[0024] 1. Determine the thickness of the device chip;

[0025] 2. Use SRIM or Geant4 software to calculate the number of vacancies generated by a single irradiated particle in the chip material, and determine the type and energy of the irradiated particle:

[0026] The type of irradiated particles is required to be particles with atomic number not less than 6;

[0027] The energy of irradiated particles is determined by the energy that the number of vacancies produced by a single irradiated particle is greater than 1000;

[0028] In the simulation process, the device chip needs to input the chemical composition elements and the thickness of each layer of the material used, and input the type and energy of the irradiated particles. When the number of vacancies produced by a single particle of the irradiated particle is greater than 1000, the particle me...

specific Embodiment approach 2

[0034] In step 4 of this embodiment, the forward bias voltage U of the DLTS equipment test parameter during the deep-level transient spectrum test is P , reverse bias voltage U R It is determined by the C-V curve; the C-V curve is the curve of capacitance changing with the applied voltage.

[0035] DLTS equipment test parameters test period t during deep level transient spectrum test w , pulse width t p Determined by a constant temperature static test to ensure that the defect is completely filled.

[0036] The scanning temperature range T of the DLTS device test parameters during the deep-level transient spectrum test is determined by the positions of different types of defect levels in the device substrate or base material.

[0037] Other steps and parameters are the same as those in the first embodiment.

Embodiment

[0039] According to the DLTS results, under normal circumstances, as the irradiation fluence increases, the defect concentration increases, and the DLTS signal peak intensity should also increase accordingly. However, if the irradiation fluence increases and the local defect concentration is too high, the Fermi level is pinned to the deep energy level, so that the shallow energy level cannot be filled by the DLTS signal, and the signal intensity of the shallow energy level DLTS peak decreases. If the phenomenon is abnormal, it proves that the pinning effect of the Fermi level has occurred.

[0040] Carry out experiment according to specific embodiment two, the result is as follows figure 1 or figure 2 shown.

[0041] figure 1 The DLTS results of SiC Schottky diodes irradiated by 40 MeV Si ions are shown. Where beforeirradiation represents the corresponding curve before irradiation.

[0042] figure 1 In the figure, with the increase of the irradiation fluence, the two ki...

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Abstract

The invention relates to a method for judging a Fermi energy level pinning effect of an electronic device and relates to a determination method for the Fermi energy level pinning effect of the electronic device. In order to solve the problem that no determination method for the Fermi energy level pinning effect of the electronic device in a particle radiation environment is generated, the method utilizes software to calculate vacancy numbers generated by a single radiation particle of radiation particles in a chip material, the type and the energy of the radiation particle are determined, radiation test is performed by selecting different radiation injection quantities, the radiation injection points are not less than 3, deep energy level transient spectrum test is performed on the deviceafter radiation, deep energy level transient spectroscopy (DLTS) curves according to different radiation injection quantities are compared, signal peaks corresponding to deep energy level defect and shallow energy level defect are compared, the device material generates Fermi energy level pinning effect if the concentration of the deep energy level defect is raised and the concentration of the shallow energy level defect is reduced with increase of the radiation injection quantity. The method is suitably used for detecting the Fermi energy level pinning effect of the electronic device.

Description

technical field [0001] The invention relates to a method for determining the Fermi level pinning effect of an electronic device. Background technique [0002] With the development of science and technology, people put forward higher and higher requirements for radiation resistance of electronic systems. The neutron radiation produced by the nuclear explosion will cause permanent damage to the semiconductor device, and the γ-ray will cause the signal in the memory to be erased or make the logic operation error. Space and spaceflight technology have increased people's activities in outer space, but cosmic rays and the Van Allen radiation belts around the earth are always challenging the reliability of electronic systems used in outer space flight. The size of the nuclear reactor used by aerospace vehicles and nuclear submarines is limited, so that the control and measurement electronic equipment used cannot be fully shielded from radiation, so improving the radiation resistan...

Claims

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Application Information

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IPC IPC(8): H01L21/336H01L21/28
CPCH01L21/28H01L29/66007
Inventor 杨剑群李兴冀李何依刘勇
Owner HARBIN INST OF TECH
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