SRAM reading-writing circuit and SRAM data accessing method

Abstract

The invention relates to an SRAM reading-writing circuit and an SRAM data accessing method. The circuit comprises an address / data control module, an address displacement chain, a data displacement chain and an SRAM memorizer array. The address / data control module receives clock signals and serial data and is used for coding the serial data in the clock signals and outputting a displacement instruction. The address displacement chain is connected to the address / data control module and used for receiving the displacement instruction of the address / data control module to conduct an address displacement operation. The data displacement chain is connected to the address / data control module and used for receiving a displacement enabling signal of the address / data control module to conduct a datadisplacement operation or used for transmitting the serial data of SRAM memorizers. The SRAM memorizer array is connected to the address displacement chain and the data displacement chain. The generation of a reading-writing control signal is completed through instruction coding, a same-clock-domain multi-stage register streamline mode is adopted in the circuit, and the circuit work efficiency isimproved.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a circuit for reading and writing SRAM and an SRAM data access method. Background technique [0002] FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) is in PAL (Programmable Array Logic, programmable array logic), GAL (Generic Array Logic, general array logic), CPLD (Complex Programmable Logic Device, complex programmable logic device) and other programmable devices based on the further development of the product. It emerged as a semi-custom circuit in the field of ASIC (Application Specific Integrated Circuit), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of original programmable device gates. [0003] SRAM (Static Random Access Memory) has the advantages of high speed, low power consumption and compatibility with standard processes, and is widely used in PCs, personal communi...

AI Technical Summary

Problems solved by technology

This patent document has the following deficiencies: first, the read and write pulses and clocks in the prior art need to perform logical operations, which will have a certain impact on the quality of the control clock, which may cause clock skew or glitches, resulting in speed bottlenecks; second, The prior art read operation uses a parallel bus, which requires more internal wiring resources for distributed SRAM, and the parallel data interface spans a longer physical distance, resulting in a large delay and may cause timing problems; third, multiple clocks need to be used For input and read / write pulse input, more port resources need to be used, and the problem of signal crossing clock domains needs to be considered

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