Method and device for fault tolerance of grading instruction memory structure capable of actively writing back

Abstract

The invention provides a method and a device for fault tolerance of a grading instruction memory structure capable of actively writing back. The device comprises a grading instruction memory, an instruction fault correcting and checking module, an instruction character register, and an instruction address register. The method comprises: 1, starting and operating a processor; 2, taking out instruction character data from the grading instruction memory; 3, sending the instruction character data to the instruction fault correcting and checking module; 4, determining a fault correcting and checking result to have no fault or have a correctable fault; if yes, continuing to perform a step 5; if no, jumping to step 10; 5, writing an instruction character to the instruction character register; 6,updating the instruction address register; 7, determining whether a correctable fault occurs; if yes, continuing to perform a step 8; if no, jumping to a step 9; 8, writing the instruction character data back to the grading instruction memory; 9, ending processing; jumping to the step 2, processing the address of the next instruction; 10, when the instruction character data has uncorrectable fault, suspending the processor. The method and the device realize fault tolerance of instructions and the instruction memory, and have relatively low hardware cost.

Description

technical field [0001] The invention belongs to the field of microprocessor design, and relates to the design of a highly reliable and high-performance processor fault-tolerant structure, in particular to a fault-tolerant method and device for a hierarchical instruction memory structure that can be actively written back. Background technique [0002] On-chip memory is a sensitive unit within the processor. On-chip memory usually occupies a large amount of area in the entire processor and is vulnerable to high-energy particles, cosmic rays, and other factors. Especially as the feature size of integrated circuits shrinks sharply, decreasing power supply voltage, increasing operating frequency, decreasing node capacitance and rapidly increasing chip transistor capacity make memory cells more and more sensitive to the working environment. Therefore, in order to improve the reliability of the processor, the on-chip memory needs to be hardened for fault tolerance. Moreover, in m...

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Problems solved by technology

In this way, the core algorithm instruction needs to have multiple control fields, and the instruction encoding field is longer; while the general instruction function is simple, the encoding field is shorter

This further increases the vulnerability of digital signal processor instructions, because once an error occurs in the field for distinguishing long and short instructions, the digital signal processor will not be able to distinguish and access subsequent instructions according to the correct width, resulting in abnormal program execution

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