Preparation method of bottom emitting top gate self-aligning thin film transistor

Abstract

The invention relates to the technical field of display, and discloses a preparation method of a bottom emitting top gate self-aligning thin film transistor. The preparation method comprises the stepsthat a light shading layer, a first buffer layer covering the light shading layer and a deposited active layer which are formed on an underlying substrate in turn. The preparation method also comprises the steps that a first metal layer is deposited on the active layer, and the active layer and the first metal layer are patterned by using a two-tone mask plate so that an active island and a metalbuffer layer are formed through the primary composition process; and source and drain electrodes are formed on the metal buffer layer. The active layer does not need to be conductive, the parasitic resistance between the channel region and the source and drain electrodes can also be effectively reduced, and the number of the mask plate is not increased so that the technological process of the device can be simplified, the production cost can be saved, the metal buffer layer and the light shading layer are cooperated to effectively prevent the influence of the light on the channel region and the LDD region, the illumination stability of the top gate device can be improved, the problem of appearing of the residual image in display can be avoided and the efficiency of the technological process and the product yield rate can be enhanced.

Description

technical field [0001] The invention relates to the field of display technology, in particular to a method for preparing a bottom-emitting top-gate self-aligned thin film transistor. Background technique [0002] In the field of semiconductor technology, compared with traditional silicon-based thin film transistors (Si-TFTs), metal oxide thin film transistors represented by IGZO (indium gallium zinc oxide) TFTs (thin film transistors) are characterized by their high mobility, manufacturing process The advantages of simplicity, low cost, and large-area uniformity have been developed rapidly, and have become key devices for driving OLED (organic light-emitting diode) display panels. [0003] At present, in order to realize the characteristic of small parasitic capacitance required for higher-resolution OLED display, IGZO TFT adopts a top-gate self-aligned structure, but the main problem is how to reduce the distance between the channel region and the source-drain electrode. p...

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Problems solved by technology

[0003] At present, in order to realize the characteristic of small parasitic capacitance required for higher-resolution OLED display, IGZO TFT adopts a top-gate self-aligned structure, but the main problem is how to reduce the distance between the channel region and the source-drain electrode. parasitic resistance, such as figure 1 As shown, the parasitic resistance R between the channel region A and the source and drain electrodes 01 P Including the resistance R of the LDD region (lowly doped drain region) B LDD and the contact resistance R between the source and drain electrodes 01 and the active layer 02 C ; The second is how to improve the light stability of the top-gate device. Since the oxide itself is sensitive to light, the electrical characteristics of the oxide material will change under light; in order to reduce the parasitic between the channel region A and the source-drain electrode 01 resistance, it is necessary to process the area where the active layer 02 is in contact with the source and drain electrodes 01 through Ar (argon), He (helium) and other gas plasmas, that is, the process of realizing the conductorization of the active layer, but the process of conductorization of the active layer exists The process is complicated, the device mobility is low, and the stability is poor. In order to improve the light stability of the top-gate device, a layer of light-shielding layer 03 is usually formed on the substrate 04 to play the role of light-shielding

However, the light-shielding layer 03 cannot completely and effectively isolate the influence of light on the channel region A and the LDD region B, which makes the TFT prone to large threshold voltage drift, which exceeds the compensation range of the compensation circuit, resulting in a series of problems such as afterimages during display.

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