Complementary nanowire semiconductor device and preparation method thereof

Abstract

The invention provides a complementary nanowire semiconductor device and a preparation method thereof. The preparation method comprises steps of providing a substrate on which an NMOS active region, a PMOS active region, and a shallow trench isolation region are formed; selectively epitaxially growing the germanium crystal material on the NMOS active region and the PMOS active region to form a first polygonal epitaxy; selectively etching the substrate to suspend the first polygonal epitaxial line above the substrate; selectively epitaxially growing Group III-V semiconductor crystalline material in a peripheral region of the first polygonal epitaxy over the NMOS active region to form a second polygonal epitaxy; depositing a dielectric material on the first polygonal epitaxy and the second polygonal epitaxy, wherein the dielectric material covering the first polygonal epitaxy and the second polygonal epitaxy; and depositing a conductive material on the dielectric material to form a gate electrode surrounding the first polygonal epitaxy and the second polygonal epitaxy, wherein the first polygonal epitaxy acting as a first nanowire, and the second polygonal epitaxy acting as a second nanowire.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a complementary nanowire semiconductor device and a preparation method thereof. Background technique [0002] With the continuous innovation of portable electronic products, its process technology is also constantly improving, and the miniaturization of product size is currently the most concerned technology, such as the continuous miniaturization of metal oxide field effect transistors (MOSFET), However, the miniaturization of transistors leads to many physical limitations and problems, such as hot carrier injection, leakage current, insulation, short-channel effects (Short-Channel Effects, SCEs) and channel length control, etc., making the gate of the transistor The ability of the pole to control the channel gradually decreases. [0003] Therefore, in order to solve the problems caused by the miniaturization of transistors, a multi-gate (Multi-Gate) transis...

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Problems solved by technology

Although germanium can be gathered towards the center to form germanium nanowires through the subsequent oxidation thermal annealing treatment, due to the high silicon content of the inner core, that is, the low germanium content of the nanowires, this will affect the performance of the formed semiconductor device

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