Edge detection method and system and clock and data recovery circuit based on FPGA (Field Programmable Gate Array)

Abstract

The invention discloses an edge detection method and system and a clock and data recovery circuit based on an FPGA (Field Programmable Gate Array), and relates to the technical field of communication. The method comprises the following steps: performing over-sampling and delay processing on a received data signal by a local reference clock, and generating a rising edge pulse signal and a falling edge pulse signal based on the data signal being subjected to the over-sampling and delay processing, wherein the rising edge pulse signal comprises a plurality of rising edge pulses, and the falling edge pulse signal comprises a plurality of falling edge pulses; performing statistics to obtain the quantity N of local reference clock periods after the rising edge pulses and the quantity M of the local reference clock periods after the falling edge pulses respectively; and judging that the rising edge pulses are valid rising edge pulses when (M-N) is greater than a set threshold, and judging that the falling edge pulses are valid falling edge pulses when (N-M) is greater than the threshold. Through adoption of the edge detection method and system and the clock and data recovery circuit, the valid rising edge pulses and the valid falling edge pulses can be detected, and the accuracy and reliability of data signal sampling are improved.

Description

[0001] The invention relates to the technical field of communication, in particular to an edge detection method, system and clock data recovery circuit. Background technique [0002] With the development of communication technology and electrical signal processing technology, serial data communication is widely used in telecommunications, optical transceivers, data storage area networks and wireless products, and the transmission rate is getting faster and faster. In serial data communication, in order to save overhead, generally only the data signal is transmitted without the clock signal synchronized with the data signal, that is, at the sending end, the clock is embedded into the data, and at the receiving end, clock data recovery (Clock and Data Recovery) is used. The Data Recovery (CDR) circuit extracts the clock from the received data, and then uses the clock to "retime" the data to eliminate the jitter accumulated during transmission. A CDR circuit based on a phase lock...

AI Technical Summary

Problems solved by technology

A CDR circuit based on a phase locked loop (PLL) can realize phase tracking and synchronization between the local reference clock and data, but for burst signals, the PLL cannot meet the requirements of fast synchronization, and a large phase Changes can cause loss of lock, and the lock time is usually very long, unable to quickly capture the phase change of the received data

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