Scan chain re-sequencing method

Abstract

The embodiment of the invention discloses a scan chain re-sequencing method and is applied to the technical field of an integrated circuit scanning test. In the embodiment, registers forming a scan chain are sorted according to clock tress delay from big to small, then the scan chain is segmented and recombined, and the length of the recombined scan chain is calculated and adjusted till the chain length is shorter. Clock deviations among the registers can be considered according to the embodiment, the number of the inserted registers can be decreased to the greatest extent under the situation that time constraints kept among the adjacent registers are met, the area occupied by the scan chain can be decreased, the problem of wire arrangement congestion can be relieved, and the overall power consumption of circuits can be reduced. No side effect is played on the testing time and scan coverage rate of the scan chain, and the process influence on the design is smaller.

Description

technical field [0001] The invention relates to the technical field of integrated circuit testing, in particular to a scanning chain reordering method. Background technique [0002] Inserting scan chains is an important method for testability design of integrated circuits. It replaces ordinary registers in integrated circuits with scan registers, and connects the scan registers end to end to form a serial scan chain to achieve additional scan test functions. The insertion of the scan chain will increase the area and power consumption of the integrated circuit, and in the test mode, the data path of the scan chain must also meet the timing check constraints such as setup time and hold time, so the buffer introduced further increases the integration Circuit area and power overhead. [0003] Reordering the scan chain is a way to reduce the area and power consumption of the integrated circuit. The scan chain reordering method is to reconnect the scan registers on the scan chain...

AI Technical Summary

Problems solved by technology

Although the existing resequencing method has achieved certain results in reducing circuit power consumption, it has brought another problem, that is, wiring congestion, and with the development of integrated circuit technology, the circuit integration level is getting higher and higher. When the process node of integrated circuit design is reduced to below 65nm, in order to meet the setup time and hold time constraints of the scan chain, more and more buffer units are required on the scan chain, resulting in more and more area and power consumption overhead , resulting in more and more severe layout and routing congestion, which adversely affects chip performance, power consumption, and area

Images