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SOI-LIGBT device capable of suppressing Snapback phenomenon and manufacturing method thereof

A technology of devices and phenomena, applied in the field of SOI-LIGBT devices and their manufacturing, can solve problems affecting device performance and achieve the effects of reducing device area, reducing device cost, and uniform distribution

Inactive Publication Date: 2017-06-13
UNIV OF ELECTRONIC SCI & TECH OF CHINA +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

A technical solution to this problem is the reverse conduction insulated gate bipolar transistor (RC-IGBT), but this solution will introduce a new problem to the IGBT, that is, the negative resistance (Snapback) effect, which will affect the performance of the device

Method used

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  • SOI-LIGBT device capable of suppressing Snapback phenomenon and manufacturing method thereof
  • SOI-LIGBT device capable of suppressing Snapback phenomenon and manufacturing method thereof
  • SOI-LIGBT device capable of suppressing Snapback phenomenon and manufacturing method thereof

Examples

Experimental program
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Effect test

Embodiment 1

[0058] Such as figure 2 as shown, figure 2 It is a schematic diagram of an SOI-LIGBT device capable of suppressing the Snapback phenomenon in this embodiment; its cell structure includes a substrate 1, a buried oxide layer 2 on the upper surface of the substrate 1, a thick dielectric layer 3 above the buried oxide layer 2, a thick The thick silicon layer drift region 4 on the left side of the dielectric layer 3, the P well region 12 at the left end inside the thick silicon layer drift region 4, the mutually independent P-type heavily doped emitter region 11 and the first P well region 12 arranged inside the P well region An N-type heavily doped region 42, an N-type buffer region 41 disposed at the right end of the thick dielectric layer 3 along the longitudinal direction, a P-type heavily doped collector region 13 at the left end inside the N-type buffer region 41, and an N-type buffer region 41 The second N-type heavily doped region 45 at the inner right end, the collector...

Embodiment 2

[0075] Such as image 3 As shown, this embodiment is basically the same as Embodiment 1, the difference is that: the collector dielectric barrier layer 31 in this embodiment includes a plurality of sub-barrier layers separated by N-type buffer regions 41 in the Z direction, adjacent sub-barrier layers The distance between the barrier layers in the Z direction is a.

Embodiment 3

[0077] Such as Figure 4 As shown, this embodiment is basically the same as Embodiment 1, with the difference that: in this embodiment, the N strips 44 and the P strips 14 are not in contact with the upper surface of the buried oxide layer 2 .

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Abstract

The invention provides an SOI-LIGBT device capable of suppressing a Snapback phenomenon and a manufacturing method thereof. The cellular structure of the SOI-LIGBT device comprises a substrate, a buried oxygen layer, a thick dielectric layer, a thick silicon layer drift region, a P well region, a P-type heavily doped emitter region, a first N-type heavily doped region, a N-type buffer region, a P-type heavily doped collector region, a second N-type heavily doped region, a collector dielectric barrier layer, a collector contact electrode, a ultrathin top layer silicon drift region, a P emitter contact electrode, a gate oxide layer, a polysilicon gate, P strips, and N strips. The N strips and the P strips are alternately arranged in the thick silicon layer drift region in the Z direction. The ultrathin top layer silicon drift region enhances the buried layer electric field to improve the longitudinal breakdown voltage of the SOI device. The thick silicon layer drift region reduces the specific on-resistance of the device. Lateral linear variable doping is performed on the ultrathin top layer silicon drift region and the thick silicon layer drift region to adjust the surface electric field distribution so that the specific on-resistance is greatly reduced while the high breakdown voltage of the device is maintained.

Description

technical field [0001] The invention belongs to the technical field of semiconductor power devices, and in particular relates to an SOI-LIGBT device capable of suppressing the Snapback phenomenon and a manufacturing method thereof. Background technique [0002] Compared with conventional bulk silicon technology, SOI technology has the advantages of high speed, low power consumption, high integration, small parasitic effect, good isolation characteristics, small latch-up effect and strong radiation resistance, which makes the reliability and anti-software of integrated circuits The ability to make mistakes has been greatly improved, and it is gradually becoming the mainstream technology for manufacturing integrated circuits with high speed, low power consumption, high integration and high reliability. [0003] Lateral Insulated Gate Bipolar Transistor (LIGBT: Lateral Insulated Gate Bipolar Transistor) has the advantages of high input impedance, voltage control, and low on-res...

Claims

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Application Information

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IPC IPC(8): H01L29/06H01L21/331H01L29/739
CPCH01L29/7393H01L29/0619H01L29/0623H01L29/66325
Inventor 乔明詹珍雅章文通肖倩倩王正康余洋何逸涛张波
Owner UNIV OF ELECTRONIC SCI & TECH OF CHINA
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