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GeOI (Ge-on-insulator) structure and preparation method

A composite and germanium layer technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems that the preparation method needs to be improved

Inactive Publication Date: 2017-03-22
TSINGHUA UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] However, the current GeOI structure and its preparation methods still need to be improved

Method used

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  • GeOI (Ge-on-insulator) structure and preparation method
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  • GeOI (Ge-on-insulator) structure and preparation method

Examples

Experimental program
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Effect test

Embodiment 1

[0078] (1) Using reduced pressure chemical vapor deposition technology, SiH 4 and GeH 4 As a gas source, using a 12-inch silicon polished wafer as a substrate, first epitaxially form a germanium transition layer. During epitaxy, the substrate temperature is first 400 degrees Celsius for 30 minutes to form a Ge epitaxial seed layer with a thickness of about 30 nm and control the punching dislocation density. Raise the temperature to 750 degrees Celsius to form a germanium transition layer (the transition layer contains a Ge epitaxial seed layer) with a thickness of about 1.5 microns. Then in the same equipment, lower the temperature to 600 degrees Celsius to form a germanium layer of about 200nm. Then the temperature was raised to 825 degrees Celsius, and at the same time hydrogen was passed through for annealing for 120 minutes, so as to improve the smoothness of the germanium surface and facilitate subsequent bonding. In this way the first complex is obtained.

[0079] (2)...

Embodiment 2

[0083] (1) Using reduced pressure chemical vapor deposition technology, SiH 4 and GeH 4 As a gas source, using a 12-inch silicon polished wafer as the substrate, first epitaxially form a germanium transition layer. During epitaxy, the substrate temperature is first 400 degrees Celsius for 30 minutes to form a Ge epitaxial seed layer with a thickness of about 30nm and control the punching dislocation density. Raise the temperature to 750 degrees Celsius to form a germanium transition layer (the transition layer contains a Ge epitaxial seed layer) with a thickness of about 1.5 microns. The temperature is raised to 825 degrees Celsius, and at the same time hydrogen is passed through for annealing for 120 minutes, so as to improve the smoothness of the surface of the germanium transition layer, which is beneficial to the subsequent bonding. In the same equipment, the temperature is lowered to 500 degrees Celsius to form 20nm thick Si 0.3 Ge 0.7 strain layer. Then, in the same ...

Embodiment 3

[0088] (1) Using reduced pressure chemical vapor deposition technology, SiH 4 and GeH 4 As a gas source, using a 12-inch silicon polished wafer as the substrate, first epitaxially form a germanium transition layer. During epitaxy, the substrate temperature is first 400 degrees Celsius for 30 minutes to form a Ge epitaxial seed layer with a thickness of about 30nm and control the punching dislocation density. Raise the temperature to 750 degrees Celsius to form a germanium transition layer (the transition layer contains a Ge epitaxial seed layer) with a thickness of about 1.5 microns. The temperature is raised to 825 degrees Celsius, and at the same time hydrogen is passed through for annealing for 120 minutes, so as to improve the smoothness of the surface of the germanium transition layer, which is beneficial to the subsequent bonding. In the same equipment, the temperature is lowered to 500 degrees Celsius to form 20nm thick Si 0.3 Ge 0.7 strain layer. In the same equipm...

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Abstract

The invention discloses a GeOI (Ge-on-insulator) structure and a preparation method. The method comprises the steps of: (1) forming a germanium transition layer and a germanium layer on the upper surface of a substrate in sequence to obtain a first complex; (2) injecting ions containing hydrogen ions to the first complex; (3) bonding the first complex with the substrate to obtain a second complex, wherein an insulating layer is formed on the upper surface of the substrate, and the insulating layer contacts the germanium layer in the bonding process; and (4) peeling the second complex to obtain a third complex and the GeOI structure respectively. The method is simple in operation and low in requirement for equipment, and can avoid size limit to the GeOI structure due to too small size of a Ge wafer for preparing the GeOI structure.

Description

technical field [0001] The invention relates to the field of semiconductor technology and semiconductor manufacturing, in particular, the invention relates to a GeOI structure and a preparation method. Background technique [0002] With the development of semiconductor technology, the feature size of Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) has been continuously reduced and its operating speed has been continuously increased. However, silicon integrated circuits based on "Moore's law" (Moore's law) have developed rapidly for decades. For Si-based materials, current MOSFET devices are close to the dual limits of physics and technology. Therefore, in order to further improve the performance of the MOSFET device, those skilled in the art have proposed various methods for improving the performance of the MOSFET device. High-mobility channel engineering based on heterogeneous material structures, especially high-carrier mobility material systems such as Si-base...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/762
CPCH01L21/76254
Inventor 王敬孙川川梁仁荣许军
Owner TSINGHUA UNIV
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