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How to form a mos transistor

A MOS transistor and layer-forming technology, applied in semiconductor devices, electrical components, circuits, etc., can solve the problems of MOS transistor carrier mobility decrease, device performance impact, etc., to prevent metal diffusion, improve performance, and save time. Effect

Active Publication Date: 2019-03-12
SEMICON MFG INT (SHANGHAI) CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Moreover, the carrier mobility of the MOS transistor is also reduced due to the diffusion of aluminum, and the device performance is greatly affected.

Method used

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  • How to form a mos transistor
  • How to form a mos transistor
  • How to form a mos transistor

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Experimental program
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Effect test

Embodiment Construction

[0031] The inventors found that the aluminum in the metal gate has two diffusion routes, one is to diffuse downward through the bottom of the metal aluminum gate (that is, it diffuses downward through the top of the channel region), and the other is to diffuse through both sides of the metal aluminum gate. diffusion. Although, in the existing MOS transistor formation method, a diffusion barrier layer is first formed in the groove for filling the metal gate before making the metal gate to prevent aluminum from diffusing, however, the diffusion barrier layer produced by the existing method usually There will be a large shrinkage stress (especially the diffusion barrier layer formed by physical vapor deposition method, the stress is relatively large), under the action of stress, the diffusion barrier layer will appear thick at the center of the bottom of the groove, and the two sides of the groove will be thick. In the case where the thickness of the side bottom corner part gradu...

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Abstract

The invention provides an MOS transistor forming method, which comprises the steps of providing a semiconductor substrate; forming a pseudo grid structure on the semiconductor substrate, wherein the two sides of the pseudo grid structure are provided with foot-shaped bottoms; forming an interlayer dielectric layer on the semiconductor substrate at the periphery of the pseudo grid structure, wherein the upper surface of the interlayer dielectric layer is flush with the upper surface of the pseudo grid structure; removing the pseudo grid structure to form a groove, wherein the two sides of the groove are provided with foot-shaped bottom corners; forming an interface layer at the bottom of the groove; forming a high-k dielectric layer at the bottom and the side wall of the groove, wherein the high-k dielectric layer covers the interface layer; forming a first diffusion barrier layer on the high-k dielectric layer; subjecting the part of the first diffusion barrier layer that is right facing the notch part of the groove to ion bombardment treatment through the sputtering process; after the ion bombardment treatment, forming a second diffusion barrier layer on the first diffusion barrier layer. The method improves the performance of an MOS transistor.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a MOS transistor. Background technique [0002] With the continuous improvement of the integration of semiconductor devices, when making MOS transistors, using high-k (high dielectric constant) materials as the gate dielectric layer and metal materials as the gate has become the mainstream technology for semiconductor device manufacturing. [0003] Existing MOS transistors with a metal gate-high-k dielectric layer structure can be formed by gate-first and gate-last methods. However, no matter which method is used, the phenomenon of metal diffusion in the metal gate will be encountered. [0004] Especially when aluminum is used as the metal gate, the diffusion of aluminum becomes a major problem in the fabrication of MOS transistors. The diffusion of aluminum will damage the reliability performance of the device, such as damage to the time dependen...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/28
CPCH01L29/401H01L29/4236
Inventor 李勇
Owner SEMICON MFG INT (SHANGHAI) CORP
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