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Domestic BMC (baseboard management controller) chip based SM4 algorithm IP (intellectual property) core design method

A BMC chip and design method technology, applied in the direction of internal/peripheral computer component protection, etc., can solve the problems that cannot meet the operation speed requirements of large data files, server security cannot be guaranteed, increase the layout space of the server motherboard, etc., and achieve saving Hardware cost, compensation limitations, effect of security guarantees

Inactive Publication Date: 2016-12-14
LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] 1. The use of additional TCM chips increases the cost, also increases the layout space of the server motherboard, and increases additional expenses;
[0006] 2. The SM4 algorithm provided by the TCM chip has poor performance, and the encryption and decryption operation speed is less than 1Mbps, so it cannot meet the operation speed requirements for large data files;
[0007] 3. From the perspective of trusted computing technology, due to the limitations of the design of the TCM module itself, BMC cannot continue to call the SM4 algorithm of TCM after successfully measuring the BIOS of the motherboard, so it cannot meet the requirements of trusted computing technology for the establishment of a trust chain. safety is not guaranteed

Method used

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  • Domestic BMC (baseboard management controller) chip based SM4 algorithm IP (intellectual property) core design method
  • Domestic BMC (baseboard management controller) chip based SM4 algorithm IP (intellectual property) core design method
  • Domestic BMC (baseboard management controller) chip based SM4 algorithm IP (intellectual property) core design method

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Experimental program
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Embodiment 1

[0048] Such as figure 1 As shown, a design method based on the SM4 algorithm IP core of the domestic BMC chip, the method adopts the SM4 symmetric cryptographic algorithm suitable for commercial cryptographic applications issued by the State Cryptography Administration in the selection of the cryptographic algorithm, which has high security and is convenient Autonomous and controllable;

[0049] The specific design adopts the hardware description language Verilog to design and realize the SM4 algorithm, and package it into a hardware IP core and integrate it into the domestic BMC chip. The AMBA bus is connected to the ARM processor in the domestic BMC chip, which makes the design flexible and convenient, and can meet the application requirements for data calculation in the field of information security.

Embodiment 2

[0051] Such as figure 2 As shown, on the basis of Embodiment 1, all signals of the encapsulation interface of the SM4 algorithm IP core described in this embodiment are clock-synchronized, sampled on the rising edge, and active at a high level. Each signal and its functions are as follows:

[0052] clk: input signal, the clock of the AMBA bus, as the clock signal of the IP core;

[0053] reset: input signal, which is the reset signal of the IP core;

[0054] Data_in[127..0]: input signal, 128 bit data input;

[0055] address[4..0]: input signal, address bus, register for selecting IP core after decoding;

[0056] op[1..0] : input pin, function selection flag, when op=0, select write key operation; when op=1, select encryption operation; when op=2, select decryption operation;

[0057] Data_out[127..0]: output signal, 128 bit operation result output;

[0058] done: output pin: a completion flag generated when each data packet operation is completed, active high.

Embodiment 3

[0060] On the basis of embodiment 1 or 2, the SM4 algorithm IP core described in the present embodiment comprises 4 registers, and word length is 32 bit, and the function of each register is as follows:

[0061] 1) Key register: the offset address is 0x00-0x07, which is used to store the user key during SM4 encryption or decryption, and only write operations can be performed on this register;

[0062] 2) Data register: the offset address is 0x08-0x0B, which is used to store a plaintext group or ciphertext group data (128bit) of the SM4 algorithm, and only write operations can be performed on this register;

[0063] 3) Operation result register: the offset address is 0x10-0x13, which is used to store the operation result of a plaintext group or ciphertext group of the SM4 algorithm, and this register can only be read;

[0064] 4) Control register: The offset address is 0x14, which can read and write the control register, so as to control the function of the SM4 algorithm IP cor...

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Abstract

The invention discloses a domestic BMC (baseboard management controller) chip based SM4 algorithm IP (intellectual property) core design method. The method includes that an SM4 symmetric cryptographic algorithm is adopted from selection of cryptographic algorithms, the SM4 algorithm is realized by adopting hardware description language Verilog in specific design and is encapsulated into hardware IP core integrated into a domestic BMC chip, an interface of the IP core adopts the form in line with AMBA (advanced microcontroller bus architecture) bus interface specifications of ARM (advanced RISE machines), and the SM4 algorithm IP core is connected to an ARM processor in the domestic BMC chip through the AMBA bus. By the adoption of the SM4 algorithm IP core, high speed and safety can be achieved, requirements on protocols of IPMI (intelligent platform management interface), SSL (security sockets layer) and the like of the BMC can be met, integration level is high, hardware logic resources of the BMC chip are effectively utilized, extra costs of hardware cost and a mainboard are saved, requirements in establishment of trust chains of the trusted computing technology are met, and limitation of a TCM (terminal-to-computer multiplexer) itself is effectively made up.

Description

technical field [0001] The invention relates to the technical field of IP core design, in particular to a design method of an SM4 algorithm IP core based on a domestic BMC chip. Background technique [0002] The domestic BMC chip is a baseboard management controller chip, which has been widely used in the server field. It uses virtual keyboards, interfaces, mice, power supplies, etc. to provide remote management functions for servers. Users can remotely monitor the physical characteristics of the server through the network port of the BMC, such as the temperature, voltage, fan working status, power supply, and chassis intrusion of each component. [0003] In the existing domestic BMC chip technology, the symmetric encryption algorithm used is RC4, and its main function is to meet the security requirements of the IPMI protocol and SSL protocol running on the BMC. The disadvantage is that the security of the RC4 algorithm is poor. It has been cracked, so there is a security r...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F21/72
CPCG06F21/72
Inventor 苏振宇
Owner LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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