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High-voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor

An oxide semiconductor, lateral double diffusion technology, applied in semiconductor devices, semiconductor/solid state device manufacturing, transistors, etc., can solve problems such as increasing process complexity and process cost

Active Publication Date: 2016-08-03
CSMC TECH FAB2 CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0002] The traditional Ptype Lateral Double-diffused Metal Oxide Semiconductor field effect transistor (PtypeLateralDouble-diffusedMetalOxideSemiconductorfieldeffecttransistor, PLDMOS) structure requires a certain length of low-doped P-type drift region to achieve high voltage resistance, so in the high-voltage NLDMOS (N-type lateral double-diffused metal Oxide semiconductor field effect transistor) and PLDMOS high-voltage integration process, need to add a low-doped P-type region photolithography, which increases the process complexity and process cost

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Embodiment Construction

[0015] In order to make the objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings. In this specification and drawings, reference signs N and P assigned to layers or regions indicate that these layers or regions include a large number of electrons or holes, respectively. Further, the reference marks + and − assigned to N or P indicate that the concentration of the dopant is higher or lower than in layers not so assigned to the marks. In the following description of the preferred embodiments and the drawings, similar components are assigned similar reference numerals and redundant descriptions thereof are omitted here.

[0016] A high-voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor, including a substrate, an N-type lateral double-diffused metal oxide semiconductor field effect transisto...

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Abstract

The invention discloses a high-voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor comprising a substrate, an N-type lateral double-diffused metal oxide semiconductor field effect transistor formed on the substrate, and a P-type metal oxide semiconductor field effect transistor formed on the drain of the N-type lateral double-diffused metal oxide semiconductor field effect transistor. The gate of the P-type metal oxide semiconductor field effect transistor is used as the gate of the high-voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor, the drain of the P-type metal oxide semiconductor field effect transistor is used as the drain of the high-voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor, and the source of the N-type lateral double-diffused metal oxide semiconductor field effect transistor is used as the source of the high-voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor. The high-voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor has the advantages of simple process, low cost, and resistance to high voltage.

Description

technical field [0001] The invention relates to the technical field of semiconductor preparation, in particular to a high-voltage P-type lateral double-diffusion metal oxide semiconductor field effect transistor. Background technique [0002] The traditional Ptype Lateral Double-diffused Metal Oxide Semiconductor field effect transistor (PtypeLateralDouble-diffusedMetalOxideSemiconductorfieldeffecttransistor, PLDMOS) structure requires a certain length of low-doped P-type drift region to achieve high voltage resistance, so in the high-voltage NLDMOS (N-type lateral double-diffused metal Oxide Semiconductor Field Effect Transistor) and PLDMOS high-voltage integration process, it is necessary to add a low-doped P-type region photolithography, which increases the process complexity and process cost. figure 1 It is a schematic diagram of the structure of a traditional PLDMOS. Such as figure 1 As shown, in order to achieve high voltage resistance and integration with high volta...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L29/423
CPCH01L29/42368H01L29/7817H01L29/7831H01L29/7835H01L29/0878H01L21/823814H01L27/0922H01L29/423H01L29/517H01L29/7816H01L21/8238H01L27/092H01L29/0649H01L29/0865H01L29/0882H01L29/1079H01L29/1095H01L29/36H01L29/4916H01L29/66681
Inventor 张广胜张森卞鹏胡小龙
Owner CSMC TECH FAB2 CO LTD
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