Multi-chip multi-matching tiled sandwiched core package structure with partial framework exposed and process method of structure

Abstract

The invention relates to a multi-chip multi-matching tiled sandwiched core package structure with partial framework exposed and a process method of the structure. The method comprises the following steps of 1, providing a first lead frame; 2, coating the first lead frame with solder paste; 3, implanting a first die and a second die onto the solder paste coating a paddle region of the first lead frame in the step 2; 4, providing a second lead frame, and coating the second lead frame with the solder paste; 5, laminating the second lead frame on the first die and the second die on the upper surface of the first lead frame, wherein the first lead frame and the second lead frame form an integrated framework after lamination; 6, pressing the upper surface and the lower surface of the integrated framework formed in the step 5 with press plates to carry out reflow soldering; 7, carrying out plastic package with a plastic package material; and 8, carrying out cutting or punching operation. The structure and the method have the advantages that the heat dissipation capability of a product is improved, and the package resistance of the product is reduced; and moreover, the whole product can be integratedly formed, and the production efficiency is high.

Description

technical field [0001] The invention relates to a partially frame-exposed multi-chip multi-lapping sandwich packaging structure and a process method thereof, belonging to the technical field of semiconductor packaging. Background technique [0002] In recent years, with the continuous pursuit of power density in electronic products, whether it is Diode (secondary tube) or Transistor (transistor) packaging, especially the MOS products in Transistor are moving towards higher power, smaller size, faster , The trend of better heat dissipation is developing. The one-time manufacturing method of packaging is also gradually sprinting and challenging from single-chip packaging technology to high-density, high-difficulty and low-cost one-time packaging technology in small areas or even larger areas. [0003] Therefore, the packaging of MOS products has been improved in terms of various electrical properties such as parasitic resistance, capacitance, and inductance, packaging structu...

AI Technical Summary

Problems solved by technology

This MOS packaging structure replaces the bonding wires in the traditional MOS packaging with metal splints, which reduces part of the packaging resistance, but there are still the following defects: First, the drain, source and gate of the chip in this MOS packaging structure are formed with the lead frame. Different devices are required for interconnection, the manufacturing process is complicated, and the purchase cost of the devices is high; secondly, when the metal splint and metal bonding wires are coupled to the chips and pins in this MOS packaging structure, it can only be done one by one. It cannot be integrally formed in one piece, and the manufacturing efficiency is low

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