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Multi-chip multi-matching tiled sandwiched core package structure with partial framework exposed and process method of structure

A technology of flat sandwich and packaging structure, which is applied in semiconductor/solid-state device parts, electrical components, electric solid-state devices, etc. It can solve the problems of high equipment purchase cost, inability to form one piece, low manufacturing efficiency, etc., and achieve equipment saving The effect of purchase, reduction of interconnection process, and improvement of production efficiency

Inactive Publication Date: 2016-06-01
JCET GROUP CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This MOS packaging structure replaces the bonding wires in the traditional MOS packaging with metal splints, which reduces part of the packaging resistance, but there are still the following defects: First, the drain, source and gate of the chip in this MOS packaging structure are formed with the lead frame. Different devices are required for interconnection, the manufacturing process is complicated, and the purchase cost of the devices is high; secondly, when the metal splint and metal bonding wires are coupled to the chips and pins in this MOS packaging structure, it can only be done one by one. It cannot be integrally formed in one piece, and the manufacturing efficiency is low

Method used

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  • Multi-chip multi-matching tiled sandwiched core package structure with partial framework exposed and process method of structure
  • Multi-chip multi-matching tiled sandwiched core package structure with partial framework exposed and process method of structure
  • Multi-chip multi-matching tiled sandwiched core package structure with partial framework exposed and process method of structure

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Embodiment Construction

[0060] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

[0061] As shown in Fig. 6(a) to Fig. 6(h), in this embodiment, a process method in which part of the frame is exposed, multi-chips and multi-layer tiled sandwich packaging structure, the specific process steps are as follows:

[0062] Step 1, see Figure 6(a), provide the first lead frame, the material of the first lead frame is alloy copper material, pure copper material, aluminum copper plated material, zinc plated copper material, nickel-iron alloy material, or other CTE The range is 8*10^-6 / ℃~25*10^-6 / ℃ conductive material;

[0063] Step 2. Referring to Figure 6(b), apply solder paste on the base island area of ​​the first lead frame by screen printing. The purpose is to realize the bonding with the base island after the first chip is implanted. Thickness and opening area can precisely control the thickness, area and position of solder pas...

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Abstract

The invention relates to a multi-chip multi-matching tiled sandwiched core package structure with partial framework exposed and a process method of the structure. The method comprises the following steps of 1, providing a first lead frame; 2, coating the first lead frame with solder paste; 3, implanting a first die and a second die onto the solder paste coating a paddle region of the first lead frame in the step 2; 4, providing a second lead frame, and coating the second lead frame with the solder paste; 5, laminating the second lead frame on the first die and the second die on the upper surface of the first lead frame, wherein the first lead frame and the second lead frame form an integrated framework after lamination; 6, pressing the upper surface and the lower surface of the integrated framework formed in the step 5 with press plates to carry out reflow soldering; 7, carrying out plastic package with a plastic package material; and 8, carrying out cutting or punching operation. The structure and the method have the advantages that the heat dissipation capability of a product is improved, and the package resistance of the product is reduced; and moreover, the whole product can be integratedly formed, and the production efficiency is high.

Description

technical field [0001] The invention relates to a partially frame-exposed multi-chip multi-lapping sandwich packaging structure and a process method thereof, belonging to the technical field of semiconductor packaging. Background technique [0002] In recent years, with the continuous pursuit of power density in electronic products, whether it is Diode (secondary tube) or Transistor (transistor) packaging, especially the MOS products in Transistor are moving towards higher power, smaller size, faster , The trend of better heat dissipation is developing. The one-time manufacturing method of packaging is also gradually sprinting and challenging from single-chip packaging technology to high-density, high-difficulty and low-cost one-time packaging technology in small areas or even larger areas. [0003] Therefore, the packaging of MOS products has been improved in terms of various electrical properties such as parasitic resistance, capacitance, and inductance, packaging structu...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/495H01L21/48
CPCH01L21/4821H01L23/49517H01L2224/97H01L2924/181H01L2224/32245H01L2224/371H01L2224/37124H01L2224/37147H01L2224/3754H01L2224/40245H01L2224/0603H01L2924/00012
Inventor 梁志忠刘恺周正伟王亚琴
Owner JCET GROUP CO LTD
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