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Multi-chip and single-lap stack sandwich package structure with exposed frames and technique for the multi-chip and single-lap stack sandwich package structure

A technology of packaging structure and process method, which is applied in the direction of semiconductor/solid-state device parts, semiconductor devices, electrical components, etc., can solve the problems of high equipment purchase cost, inability to form one piece, low manufacturing efficiency, etc., and achieve saving equipment purchase, reduction and exemption Effects of interconnected processes and improved productivity

Inactive Publication Date: 2016-05-25
JCET GROUP CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This MOS packaging structure replaces the bonding wires in the traditional MOS packaging with metal splints, which reduces part of the packaging resistance, but there are still the following defects: First, the drain, source and gate of the chip in this MOS packaging structure are formed with the lead frame. Different devices are required for interconnection, the manufacturing process is complicated, and the purchase cost of the devices is high; secondly, when the metal splint and metal bonding wires are coupled to the chips and pins in this MOS packaging structure, it can only be done one by one. It cannot be integrally formed in one piece, and the manufacturing efficiency is low

Method used

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  • Multi-chip and single-lap stack sandwich package structure with exposed frames and technique for the multi-chip and single-lap stack sandwich package structure
  • Multi-chip and single-lap stack sandwich package structure with exposed frames and technique for the multi-chip and single-lap stack sandwich package structure
  • Multi-chip and single-lap stack sandwich package structure with exposed frames and technique for the multi-chip and single-lap stack sandwich package structure

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Embodiment Construction

[0068] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

[0069] As shown in Fig. 7(a) to Fig. 7(m), a process method of a frame-exposed multi-chip single-lap stacked sandwich packaging structure in this embodiment, the specific process steps are as follows:

[0070] Step 1, see Figure 7(a), provide the first lead frame, the material of the first lead frame is alloy copper material, pure copper material, aluminum copper plated material, zinc plated copper material, nickel-iron alloy material, or other CTE The range is 8*10^-6 / ℃~25*10^-6 / ℃ conductive material;

[0071] Step 2. Referring to Figure 7(b), apply solder paste on the base island area of ​​the first lead frame by screen printing. The purpose is to realize the bonding with the base island after the first chip is implanted. Thickness and opening area can precisely control the thickness, area and position of solder paste;

[0072] Step 3, ref...

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Abstract

The invention relates to a multi-chip and single-lap stack sandwich package structure with exposed frames and a technique for the multi-chip and single-lap stack sandwich package structure. The technique comprises the following steps: (1) providing a first lead frame; (2) coating the first lead frame with a solder paste; (3) embedding a first chip into the solder paste of the first lead frame; (4) providing a second lead frame and coating the second lead frame with the solder paste; (5) laminating the second lead frame on the first chip; (6) carrying out reflow soldering; (7) coating the second lead frame with the solder paste; (8) embedding a second chip into the second lead frame; (9) providing a third lead frame and coating the third lead frame with the solder paste; (10) laminating the third lead frame on the second chip; (11) carrying out reflow soldering; (12) carrying out plastic packaging by a molding compound; and (13) carrying out cutting or punching operation. The multi-chip and single-lap stack sandwich package structure has the beneficial effects that the heat dissipation ability of a product is improved; and the packaging resistance of the product is reduced.

Description

technical field [0001] The invention relates to a frame-exposed multi-chip single-lap stacked sandwich packaging structure and a process method thereof, belonging to the technical field of semiconductor packaging. Background technique [0002] In recent years, with the continuous pursuit of power density in electronic products, whether it is Diode (secondary tube) or Transistor (transistor) packaging, especially the MOS products in Transistor are moving towards higher power, smaller size, faster , The trend of better heat dissipation is developing. The one-time manufacturing method of packaging is also gradually sprinting and challenging from single-chip packaging technology to high-density, high-difficulty and low-cost one-time packaging technology in small areas or even larger areas. [0003] Therefore, the packaging of MOS products has been improved in terms of various electrical properties such as parasitic resistance, capacitance, and inductance, packaging structure, h...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/495H01L21/60
CPCH01L24/83H01L23/49548H01L2224/8321H01L2224/97H01L2224/371H01L2224/37124H01L2224/37147H01L2224/3754H01L2224/40245H01L2224/48247H01L2224/73221
Inventor 梁志忠王亚琴徐赛朱悦
Owner JCET GROUP CO LTD
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