an etching method

Abstract

The invention discloses an etching method, comprising: processing a first semi-finished product used to manufacture a trench VDMOS device, the first semi-finished product includes a first substrate, and forming an epitaxial layer, in which at least a first body region is formed, in which at least a first source region and a second source region adjacent to the first source region are formed, As well as a first trench formed by etching down in the first source region and a second trench formed by etching down in the second source region, the method includes: in the first semi-finished product growing a gate oxide layer and a first polysilicon layer on the upper surface; thinning the first polysilicon layer to form a remaining polysilicon layer with a predetermined thickness; performing photolithography and etching on the remaining polysilicon layer, A first polysilicon gate is formed at least in the first trench and a second polysilicon gate is formed in the second trench.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to an etching method. Background technique [0002] VDMOS, that is, vertical double diffused metal-oxide semiconductor field effect transistor, VDMOS has the advantages of both bipolar transistors and ordinary MOS devices. Whether it is a switch application or a linear application, VDMOS is an ideal power device. VDMOS is mainly used in motor regulation. speed, inverter, uninterruptible power supply, electronic switch, hi-fi, automotive electrical appliances and electronic ballast, etc. Trench-type VDMOS adopts the trench etching technology invented in the preparation process of memory storage capacitors, so that the conductive trench changes from horizontal to vertical. Compared with the ordinary VDMOS structure, the resistance of the JFET neck area is eliminated. Therefore, the cell size is greatly increased. density, increasing the current handling capability of power ...

AI Technical Summary

Problems solved by technology

[0004] Since the trench VDMOS is designed differently for different devices, the distance between the trenches is large or small. When the distance between the trenches is small, the polysilicon gate protrusion is high, resulting in the dielectric layer deposition in the subsequent process. The layers are connected or hollow, such as figure 1 and as figure 2 As shown, therefore, the prior art solution has the technical problem that the photolithography and etching of the contact hole are difficult when the dielectric layer is connected, and there is even a technical problem that the contact hole cannot be formed when the dielectric layer is hollow.

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